ISSCC 2026 Deep Dive: How Optical Interconnect Is Breaking Through Under the AI Compute Surge — Silicon Photonics' Limits and the Next Battlefield
Updated: Oct 7
In recent years, the rapid rise of generative AI and large language models has been driving compute demand to double every six months — far outpacing the traditional Moore's Law cadence, under which processor performance and memory bandwidth double every two years.
To close such an enormous compute gap, AI clusters have scaled from thousands of XPUs to hyperscale deployments of 10,000 to 100,000. In clusters like these, compute is no longer the only pain point — the bandwidth and power bottlenecks created by moving massive amounts of data across nodes are what truly set the ceiling for AI infrastructure.
At the just-concluded IEEE International Solid-State Circuits Conference (ISSCC 2026), a ground-level revolution in optical interconnect was on full display. From Broadcom, NVIDIA and Marvell to Celestial AI, tech giants and top academic institutions alike converged on 3D heterogeneous integration, co-packaged optics (CPO) and lightweight coherent communication (Coherent-Lite).
Has conventional silicon photonics (SiPh) hit its limit? Who will dominate future scale-up networks? This article walks you through the underlying hardware architecture to explain the endgame for optical interconnect that ISSCC 2026 revealed.
1. Bandwidth Anxiety and a Materials Shift: Will 400G per Lane Be the Watershed for Silicon Photonics?
To understand the future of optical communications, we first need to understand the industry roadmap. In an ISSCC 2026 forum, networking giant Arista stated clearly that data center pluggable optical modules are moving rapidly toward 800G and 1600G, with a generational leap to 3200G (8x400G) expected in 2028.
The "106 GHz physical limit" of conventional silicon photonics As per-lane rates approach 400G PAM-4, the system needs a Nyquist frequency of roughly 106 GHz. At this extreme rate, the bandwidth bottleneck of conventional silicon photonics starts to show — both the response speed of carrier-depletion modulators and the losses in optical-to-electrical conversion fall short.
Arista pointed to a clear trend: in the 400G/lane era, new optical platforms with 100+ GHz bandwidth potential — such as indium phosphide (InP) and thin-film lithium niobate (TFLN) — will rise strongly and may gradually erode conventional silicon photonics' market share.
The low-power philosophy of "slow and wide" Arista also expressed skepticism about higher-order modulation such as PAM-6, because overly complex digital signal processing (DSP) carries a power overhead that is hard to bear. The ultimate low-power answer will be a "Slow & Wide" parallel interface architecture that eliminates high-speed SerDes. By using dense arrays of lower-rate lanes such as 50G NRZ, combined with linear drive (LPO) or CPO packaging, power-hungry DSPs and SerDes can be removed entirely — setting the tone for the chip-level packaging battle ahead.
2. The Battle Next to the XPU: CPO and 3D Packaging Approaches Proliferate
To overcome the power and signal-integrity drawbacks of conventional pluggable optics, bringing the optical engine (PIC) to within a few millimeters of the compute chip (EIC or ASIC) through 2.5D/3D packaging (CPO / in-package optical I/O) is now an industry consensus. But in actual implementation, each company took a strikingly different approach:
Broadcom: Extreme Throughput and Architectural Subtraction via "Direct Drive"
To meet the massive I/O demands of 51.2T network switches, Broadcom presented a 3D-packaged 6.4 Tb/s CPO solution based on a 7nm ASIC and silicon photonics MZMs.
Its biggest highlight is the receive-side (RX) "direct-drive TIA (transimpedance amplifier)" architecture. In conventional designs, the optical signal, once converted to electrical, still passes through multiple amplification and retiming stages; Broadcom's design lets the TIA output drive the host ASIC directly, with adaptive DSP tuning, eliminating redundant conversion stages. This "subtraction" drives energy efficiency at 106.25 Gb/s PAM-4 per lane down to a remarkable 4.2 pJ/b, holding the line on power at extreme throughput.
NVIDIA: The Power Magic of DWDM and "Half-Rate Forwarded Clocking"
Focusing on high-density scale-up interconnect between GPUs, NVIDIA introduced a 256 Gb/s DWDM (dense wavelength-division multiplexing) 3D-stacked CPO. DWDM packs multiple wavelengths into a single fiber and is a powerful way to raise bandwidth density, but it faces stringent clock-synchronization challenges.
In a conventional DWDM link, clock and data recovery (CDR) modules are extremely power-hungry, while a directly forwarded clock (FC) amplifies the TIA's thermal noise. NVIDIA's innovation is a "half-rate band-pass-filtered forwarded clock" scheme. They placed nine microring resonators in the 1310nm band (200 GHz spacing) — eight carry data and one is dedicated to the clock — and use a band-pass filter to precisely remove random noise. This architecture eliminates the power-hungry CDR and achieves an exceptionally high area efficiency of 1.33 Tbps/mm².
For a more detailed explanation, see the article below.
Celestial AI: An EAM Modulator That Tackles Thermal Stability Head-On
The biggest hidden killer of in-package optical I/O is heat. Being packaged alongside an XPU means optical components must withstand temperatures of 80°C or more. Conventional microring modulators (MRMs) are extremely temperature-sensitive — any temperature change shifts their resonance — and require substantial extra power for thermal tuning.
Celestial AI's 3D-integrated 5nm CMOS and silicon photonics transceiver boldly abandons MRMs in favor of a germanium-silicon (GeSi) electro-absorption modulator (EAM). The EAM's physics give it excellent thermal robustness: measurements show that across a steep 30°C-to-80°C swing, only a small DC bias adjustment is needed for stable operation, with no complex background calibration at all. With a single TX/RX pair occupying just 0.09 mm², this chip offers a commercially promising answer for hot AI cluster environments.
Company | Core Architecture & Process | Key Pain Point Addressed | Innovation Highlights (Architecture/Device) | Key Metrics |
Broadcom | 7nm ASIC + SiPh MZM (3D-packaged CPO) | The power and signal-conversion overhead of massive I/O in a 51.2T switch. | Direct-drive TIA architecture The RX TIA output drives the host ASIC directly, removing redundant amplification and retiming stages (architectural subtraction). | • Total throughput: 6.4 Tb/s • Per-lane rate: 106.25 Gb/s (PAM-4) • System energy efficiency: 4.2 pJ/b |
NVIDIA | 7nm EIC + 65nm PIC (DWDM 3D-stacked CPO) | In DWDM links, conventional CDR modules consume too much power, while a directly forwarded clock amplifies thermal noise and jitter. | Half-rate band-pass-filtered forwarded clock One of nine wavelengths is dedicated to the clock, and a band-pass filter precisely removes random noise, eliminating the power-hungry CDR entirely. | • Total throughput: 256 Gb/s • Wavelength plan: 1310nm (200 GHz spacing) • Area efficiency: 1.33 Tbps/mm² |
Celestial AI | 5nm CMOS + SiPh (3D-integrated transceiver) | The thermal-stability problem of conventional microring modulators (MRMs), whose resonance drifts at the 80°C-plus temperatures next to an XPU. | Germanium-silicon (GeSi) electro-absorption modulator (EAM) Replaces MRMs with an inherently thermally robust EAM. Operates stably across steep 30°C–80°C swings with only a small bias adjustment. | • Per-lane rate: 56 Gb/s (NRZ) • Single TX/RX area: 0.09 mm² • Feature: extremely low thermal-tuning power |
3. Filling a Market Gap: Coherent-Lite and Extreme Miniaturization
Beyond ultra-short-reach intra-rack interconnect, as AI compute infrastructure moves toward distributed, campus-scale architectures, 2-to-40 km data center interconnect (DCI) has become a brand-new main battlefield.
Marvell: The Comeback of Lightweight Coherent (Coherent-Lite)
At 2–40 km, conventional intensity-modulation direct-detection (IMDD, e.g., PAM-4) can't reach far enough, while conventional coherent can — but its DSP is extremely complex because it must compensate for chromatic dispersion over long fiber, resulting in excessive power and high latency (typically over 3 microseconds), which is fatal for latency-sensitive AI training.
Marvell's newly unveiled 5nm dual-channel 800 Gb/s Coherent-Lite transceiver targets exactly this pain point. They optimized the DSP algorithms specifically for the low-dispersion O-band, using a low-power 4x4 real-valued MIMO equalizer that dramatically reduces the computational load. This change compresses end-to-end latency to <300ns — an order of magnitude lower than conventional coherent modules — perfectly filling the interconnect needs of distributed AI campuses.
UCB / MediaTek / Ayar Labs: A Monolithic Transmitter That Breaks Physical Size Limits
Pushing the limits of optical interconnect miniaturization, UC Berkeley, MediaTek and Ayar Labs jointly delivered a disruptive result.
Reverse-biased PN-junction MZM modulators commonly used in silicon photonics are bulky, typically over 3 mm long, making ultra-high-density integration difficult. Building on a 45nm CMOS-SOI process, the team innovatively adopted a forward-biased PIN MZM. The PIN junction's very high modulation efficiency shrinks the modulator to just 0.4mm (a 5× reduction in chip area versus conventional designs).
However, the physical price of a forward-biased PIN junction is very low bandwidth. To fix this fatal weakness, the team added "passive RC equalization" and "transmit-side pre-emphasis (TX-FIR)" to the driver circuit, pushing bandwidth high enough to support single-wavelength 212 Gb/s 16-QAM coherent transmission, while achieving an ultra-high energy efficiency of 0.91 pJ/b. It demonstrates the powerful potential of using advanced circuit design to compensate for the physical shortcomings of optical devices.
Conclusion: Optical Interconnect Has Entered the Deep Waters of System-Level Co-Design
Looking back at these heavyweight ISSCC 2026 papers, one clear conclusion emerges: optical communications technology has moved beyond the stage of relying solely on improving the performance of individual components such as lasers or modulators.
As 400G per lane approaches the physical limits of silicon photonics, future winners will be determined by who can most deeply co-design advanced packaging (3D hybrid bonding), next-generation optical materials (TFLN / InP / GeSi), and innovative circuit and system architectures (direct drive, DWDM filtering, Coherent-Lite).
When AI progress depends so heavily on a super-brain made of tens of thousands of GPUs, optical interconnect is the synapse that links those neurons and sets the upper limit of the system's overall intelligence. The 3200G bell has already rung, and the traditional optical module supply chain faces an unprecedented technology reshuffle. For investors and technologists following semiconductors and communications infrastructure, this all-out arms race — from base materials to packaging architecture — is only now reaching its most exciting climax.
Comments