The Hidden Revolution in AI Data Centers: Interconnects Shift from “Fast and Narrow” to “Slow and Wide”

Oct 5

4 min read

Updated: Oct 7

As AI compute grows exponentially, data centers face a severe physical bottleneck: the interconnect. As GPU clusters scale up, traditional copper is approaching its limits in bandwidth density and power consumption. To meet AI training's demand for massive data exchange, optical interconnect is undergoing a paradigm shift from pluggable modules to Co-Packaged Optics (CPO).

Based on the recent paper by M. Kohli and J. Teissier, “VCSEL-based CPO for Scale-Up in A.I. Datacenter – Status and Perspectives,” this article uses its data and perspectives to examine in depth why a VCSEL-based “slow-and-wide” architecture is very likely the best solution for AI scale-up networks (short-reach interconnect).

Core concept: why do we need CPO?

Figure walkthrough: Figure 1 – the future interconnect architecture

[Figure analysis] This concept diagram shows a UCIe-compatible VCSEL array link architecture.

Left (XPU/UCIe): The AI processor (XPU) sends signals through the standard UCIe interface.
Right (Optical Engine): The signal enters the electronic IC (EIC), which directly drives the Vertical-Cavity Surface-Emitting Laser (VCSEL) array above it. The optical signal then travels vertically into lenses and multicore fibers.
Technical implications:
- Higher integration: The optical engine is no longer a separate external module; it is tightly integrated with the processor through a silicon interposer.
- Better energy efficiency: This design drastically shortens the electrical signal path and reduces transmission loss on the PCB.

The physical limits and energy cost of copper

Figure walkthrough: Figure 2 – link loss and energy cost

[Figure analysis] This chart quantifies the cost of the traditional pluggable optical module architecture.

Electrical loss (blue line): As the signal travels from the ASIC through PCB traces and vias to the pluggable module at the chassis edge, loss reaches 22 dB.
Energy cost (red line): To compensate for this loss and correct the signal, the system burns a lot of power. Just “moving” data to the optical module costs about 3.5 pJ per bit. Adding the DSP (digital signal processing) inside the module, total energy reaches 13.5 pJ/bit.
Technical implications: Copper loss at high frequency forces us to use power-hungry DSPs. If CPO can eliminate this copper segment, it saves this huge “toll.”

Technology showdown: who is the king of energy efficiency?

Figure walkthrough: Figure 3 – energy efficiency of competing technologies

[Figure analysis] This bar chart compares the estimated total energy efficiency of different CPO approaches (lower is better).

Green (VCSEL): Best performer. In particular, the 32 Gbit/s VCSEL array using the “slow-and-wide” strategy is estimated at just 0.75 pJ/bit total. Even the high-speed version (108 Gbit/s) is highly competitive in efficiency.
Blue (MicroLED): Although MicroLEDs are theoretically very power-efficient, low wall-plug efficiency (< 2%) and difficult fiber coupling put real system efficiency at about 3.6–7 pJ/bit.
Purple (SiPh, silicon photonics): Today's mainstream Broadcom/NVIDIA approaches (200G SiPh) come in at about 5–8 pJ/bit.
Technical implications: For short-reach (scale-up) links, the VCSEL, with its simple structure and no need for an external laser source, shows a better energy efficiency advantage than silicon photonics.

Signal quality: the possibility of dropping the DSP

Figure walkthrough: Figure 4 – eye diagrams and signal integrity

[Figure analysis] The eye diagram is a key indicator of digital signal quality.

(a) Good Channel: Clean lines and an open “eye” indicate excellent signal quality with no need for complex correction.
(b) Lossy Channel: The signal is attenuated by transmission loss and the eye closes, usually requiring DSP intervention.
(c) Impaired Channel: The signal is distorted by dispersion or bandwidth limits.
Technical implications: By lowering the per-lane rate, the “slow-and-wide” (WaS) architecture keeps the physical-layer signal close to state (a). That means the power-hungry, latency-adding DSP can be removed, returning to purer analog drive.

Reliability: the lifeline of AI training

Figure walkthrough: Figure 5 – redundancy and fault tolerance

[Figure analysis] AI training is extremely sensitive; any link interruption can lead to costly retraining.

(a) Failure rate curves: These show the relationship between VCSEL array failure rate (FIT rate) and the number of spare lanes. Adding just 15% spare lanes greatly improves overall link reliability, bringing the failure rate down to very low levels.
(b) 2D array repair diagram: This shows the fault-tolerance mechanism in the array. When a link fails (red cell), the system can “hot-swap” to an adjacent spare link (blue cell), keeping total bandwidth unchanged.
Technical implications: This ability to trade spatial redundancy for reliability is an advantage that conventional single-laser-source silicon photonics approaches find hard to replicate, and it effectively reduces the risk of AI training interruptions.

Summary: key metrics at a glance

Table walkthrough: Table 1 – technology specification summary

[Table analysis] This table summarizes the key metrics of each technology at 3.2T bandwidth.

Energy efficiency: The VCSEL (32 Gb/s array) wins at <0.75 pJ/bit, far below SiPh's ~5 pJ/bit.
Latency: With no DSP and no complex forward error correction (FEC), the VCSEL approach offers low latency.
Complexity: The VCSEL is a directly modulated light source; unlike SiPh it needs no external laser and ring modulators, and unlike MicroLED it doesn't face fiber-coupling challenges.

Simple Tech Trend's view

This research reveals a counterintuitive trend: for short-reach interconnect inside AI racks, “faster” isn't necessarily “better.”

Through a “slow-and-wide” strategy, lowering the per-lane rate while greatly increasing the number of lanes, combined with VCSEL technology, we can significantly cut power and improve reliability without sacrificing total bandwidth. For AI hardware architects seeking to break past the limits of Moore's Law, VCSEL CPO offers a highly promising path to green computing.