OFC 2026 | Is CPO Ready for AI Pipelines? OFC Workshop Panel with NVIDIA, Broadcom, Cisco, Oracle, Arista, AMD and Meta

Introduction: At OFC 2026, the optical communications industry's premier event, “Is co-packaged optics (CPO) ready to support AI pipelines?” emerged as the defining strategic question. Historically, IBM achieved the first commercial CPO deployment 16 years ago in its Power 775 system, shipping roughly 10,000 systems. Today, however, as AI clusters scale toward 130,000 GPUs, the physical limits of traditional copper and pluggable optical modules are fast approaching. This workshop brought together supply-chain heavyweights including Meta, Oracle, NVIDIA, Broadcom, Arista, Cisco and AMD for an unprecedented, data-heavy clash—from front-end silicon photonics component yield to back-end cluster total cost of ownership (TCO) and liquid cooling. It marks CPO's formal move from “technology showcase” into the deep waters of volume production, and foreshadows a reshaping of the 12.8T-to-51.2T network switching landscape.

Core Technologies and Data Deep Dive: Vendor Strategies and Production Track Records

In this closed-door-caliber workshop, end users (hyperscalers) and chip/system suppliers presented sharply different technical solutions and production progress.

1. Oracle: Holding the Reliability Line, Advocating Socketed CPO and Expanded Beam Technology

Oracle Distinguished Engineer Mark Filer noted that in its 130,000-GPU AI supercluster, nodes are natively equipped with 1.6T NICs and use a multi-plane scale-out architecture.

• Core pain point and CPO benefits: Network outages are fatal for costly GPU clusters. CPO eliminates failure points caused by manual module insertion and, compared with fully reconfigurable systems, can save up to 50% in power and 30% in cost.

  
  

• Architecture preference (socketed CPO): Oracle strongly rejects vertically integrated packages that lock it into a single switch ASIC vendor. It advocates socketed CPO approaches such as PPAK to simplify RMA repairs and enable a multi-vendor ecosystem.

  
  

• Optical connector innovation: To address the single-point-of-failure risk (blast radius) of up to 4,096 fibers on the front panel, Oracle explicitly backs Expanded Beam Technology, such as US Conec's Prism PNT or 3M's EBO, which can cut mating force by 20x and greatly improve immunity to dust.

2. Meta: 50 Million Device-Hours of CPO Reliability Data Made Public

Drew Alduino, Director of Optical Infrastructure at Meta, brought the field data the industry has been craving, stressing that TCO is the ultimate basis for decisions.

• Accelerated aging test data (43°C ambient):

  • 2x400G FR4 pluggable modules: 6,881.48G cumulative device-hours, with a mean time between failures (MTBF) of only 0.7 million hours.

  • Phase 1 CPO system: Reached 40 million equivalent device-hours. Including manufacturing defects in SMT components inside the pluggable laser source (PLS), MTBF is about 1.7 million hours. Excluding that serviceable failure, CPO's MTBF shows up to a 10x improvement over pluggable modules.

    
    

• Room-temperature deployment status: Meta now has Phase 2 CPO systems running in a standard 22°C environment, accumulating 50 million device-hours with an extremely low failure rate—so low that a new MTBF cannot yet be calculated precisely.

3. Arista: The Pluggable Counterattack with a 12.8T Liquid-Cooled XPO Architecture

While most major players are bullish on CPO, Arista's Vijay Vusirikala dropped a bombshell, declaring that “pluggable modules will not die.”

• XPO (Extra Dense Pluggable Optics) specs: Capacity of up to 12.8 Tbps (200G/lane), equivalent to the throughput of eight OSFP modules.

• Native liquid cooling data: Direct liquid cooling lowers component temperatures by a significant 20–25°C; combined with a lower component count, system-level reliability jumps 8x.

• Density limits: XPO delivers 204.8 Tbps in 1RU (versus 4RU with OSFP), a 4x improvement in rack density, reaching 6.4 Pbps per rack.

4. Broadcom: Tomahawk 6 CPO in Production and a Shift in Modulation Technology

Broadcom's Matt Traverso showcased the company's dominance in the CPO race.

• Davidson platform: Broadcom's third-generation CPO product and the first 100G Ethernet CPO switch built around the Tomahawk 6 (TH6) core die.

• Power data: Achieves more than 70% power reduction versus pluggable modules, while keeping the link flap error rate well below the KP4 FEC tolerance (16 bit errors).

• Core technology shift: Announced it is abandoning PAM4 modulation in favor of NRZ (or M2) encoding combined with WDM, avoiding the 4.8 dB signal-to-noise ratio (SNR) penalty that PAM4 incurs.

5. Cisco: A Cold Shower on Yield and Physical Limits—“CPO Is Inevitable, but Not Imminent”

Cisco's Anthony Torza offered a pragmatic warning from an engineering-physics perspective.

• Signal integrity (SI) limits: At the 200G generation, a 0.9mm BGA pitch already exceeds a quarter wavelength, causing severe reflection degradation. Even so, Cisco can still build a 64x OSFP (1600G) 200G/lane switch using conventional PCB routing.

• The yield trap: In a CPO system with 16 optical engines, even if each engine's attach yield reaches 95%, system yield drops to only about 44% (0.95^16).

• Thermal micro-effects: A 100% liquid-cooled system reduces airflow to 2–3 CFM, which fundamentally eliminates the dust accumulation and internal contamination caused by traditional air cooling—inadvertently improving the reliability of existing modules.

6. NVIDIA: Commercial Breakthroughs with Micro-Ring Modulators (MRM) and TSMC COUPE

NVIDIA's Amir Saheki revealed silicon photonics progress in its scale-out (NVLink/InfiniBand) architecture.

• MRM commercialization: Micro-ring modulators (MRM) are commercialized for the first time in shipping products such as Blackwell. Although MRMs are extremely temperature-sensitive, NVIDIA has solved the stability problem with sophisticated adaptive circuitry and thermal management.

• Wafer-level packaging: Uses TSMC's COUPE heterogeneous integration technology to combine a 5nm electronic IC (EIC) with a photonic IC (PIC). The process enables high-throughput electro-optical testing (EOE testing) at the wafer level, screening out defective parts early and enabling CMOS-grade cost reduction at scale.

7. AMD: Material Limits and Interface Consensus

AMD's Juthika Basak emphasized that CPO delivers a 3x improvement in energy efficiency.

• Modulator bottleneck: Because pure silicon lacks a strong electro-optic effect, both MZI and MRM designs must compromise between size and bandwidth; she called on the foundry ecosystem to introduce new material processes.

• Coupling trade-offs: Edge couplers demand extremely tight optical assembly tolerances, while grating couplers depend on foundry process tolerances—requiring close collaboration between OSATs and foundries.

Deep Dive into Consensus and Divergence

• Firm consensus 1: TCO and RAS decide everything. Every power reduction (50–70%) ultimately serves to return power to the GPUs and raise AI token output (tokens/watt). Reliability, availability and serviceability are the minimum entry threshold for AI clusters.

  
  

• Firm consensus 2: External laser sources (ELS) are essential. Since lasers are the main heat source and a potential degradation component, separating high-power lasers from the CPO package as hot-swappable modules (such as PLS) has become the standard way for vendors to shrink the “blast radius.”

  
  

• Strategic divergence 1: The transition path at the 224G generation. Oracle and Broadcom see 224G/lane as a mature entry point for CPO; Arista aims to intercept it with 12.8T liquid-cooled XPO pluggables; Cisco insists that 400G/lane is the “technical imperative” where CPO gains a decisive advantage.

  
  

• Strategic divergence 2: Package form (soldered vs. socketed). Chip vendors favor soldered-down CPO to optimize signal and packaging cost, while cloud giants (such as Oracle) strongly demand socketed or NPO architectures to secure multi-vendor supply and reduce the risk of scrapping entire boards.

  
  

Supply Chain and Market Impact

1. Value redistribution between OSATs and foundries: NVIDIA's adoption of TSMC COUPE shows that 2.5D/3D heterogeneous integration (such as hybrid bonding) has become the ultimate solution for optoelectronic integration. Packaging and test houses that cannot provide submicron optical alignment and high-throughput wafer-level EOE testing will be pushed out.

   
   

2. Standards alliances drawing battle lines: The OCI MSA (NVIDIA, AMD, Broadcom, Meta and others) is firmly leading optical specifications for scale-up, while on the scale-out side, new pluggable formats such as XPO will wage a fierce pricing war against early CPO solutions.

   
   

3. A shake-up in optical connectors: As fiber counts rise exponentially, traditional MPO physical-contact connectors are no longer adequate, and expanded beam and non-contact optical connectors are set for explosive growth.

   
   

Simple Tech Trend Editor's View

As close observers of the evolution of silicon photonics and high-speed network infrastructure, we saw at OFC 2026 that CPO has truly crossed from “science experiment” into the harsh reality of engineering yield and supply chain management.

We expect that over the next 12 to 24 months:

1. “Dual tracks in parallel” will be the norm: Ultra-high-density pluggables with native liquid cooling (such as Arista's XPO) will capture a large share of the 224G/lane-generation orders that spill over as the CPO supply chain struggles to ramp yield.

   
   

2. CPO's golden cross lands at 400G/lane: Once the physical limits of electrical traces completely shut down PCB routing, CPO—with its 70% power advantage—will take off after 2027.

   
   

3. Ecosystem convergence: Only fabless giants backed by top-tier foundries such as TSMC, and able to solve the yield challenge of attaching 16 optical engines at once, will ultimately dominate this epic battle over 130k-GPU interconnect.