Advantest (6857) FY2026 Q2 Earnings: Revenue +82%, 55.9% Operating Margin, CPUs Become the Third Pillar as SoC Tester Capacity Heads to 10,000 Units

1. Executive Takeaway

First, demand now stands on three pillars, not two. GPUs and custom ASICs are still running hot, but CEO Doug Lefever named CPUs as the single biggest driver behind this quarter's SoC tester upgrade. Inference AI is pushing the CPU-to-GPU ratio higher, server CPUs ship in huge volumes and their test times are far from trivial; this demand was simply not in anyone's model.

Second, Advantest is limited by capacity, not orders. In management's own words, the full-year raise came from capacity expanding faster than expected, so both Q3 and Q4 can ship more systems. From 5,000 units to 10,000 and then 20,000, the growth formula is now simple: whatever Advantest can build, it can sell.

Third, gross margin hit a record, but 55.9% is not the new normal. The first half benefited from DDR inventory bought at old prices and a one-time inventory reversal, while the second half faces higher DRAM spot prices, so management itself guided operating margin back to the "low 50s". The 2H outlook implies a 50.1% operating margin, about 4 points below the 54.0% of 1H. This decline is already baked into guidance, not a surprise.

2. Revenue and Financials

All figures are IFRS and in Japanese yen, taken from the company's financial results and briefing slides (FY2026 is the fiscal year ending March 2027; the Quartr transcript labels this quarter Q2 FY2027, which is the same period).

Metric	FY2026 Q2	YoY	QoQ
Revenue	¥477.7B	+81.7%	+30.0%
Gross margin	71.1%	+8.9 pts	+1.6 pts
Operating income	¥266.8B (55.9% margin)	+146.0%	+40.4%
Net income	¥193.3B	+142.7%	+10.6%
Basic EPS	¥267.75	—	—

The story in these numbers is operating leverage. Revenue grew by ¥214.8B and operating income by ¥158.3B, so roughly ¥74 of every additional ¥100 of sales dropped to operating profit. That reflects ever-richer high-end SoC tester configurations and a better product mix, and it explains why Advantest can say it reprices through new configurations, licensing and new instruments rather than straight price hikes.

By segment, SoC test systems delivered ¥353.3B in the quarter, up about 103% YoY and roughly 80% of the ¥436.7B test system business; memory test systems were ¥53.4B, up about 22%; other systems ¥29.9B; and services and others ¥41.1B, up about 61%.

Net income deserves a second look: first-half financial income was about ¥57.0B, mostly valuation gains on strategic investments (about ¥54.2B), and most of it landed in Q1. That is why Q1 net margin jumped to 47.6% before falling back to 40.5% in Q2. To judge the core business, look at operating income, not the sequential change in EPS.

▲ Advantest FY2026 Q2 key financials: revenue ¥477.7B (YoY +81.7%), gross margin 71.1%, operating margin 55.9%, net income ¥193.3B, segment revenue and 2H outlook ¥1,017.8B (Image source: Simple Tech Trend original; data from Advantest FY2026 Q2 financial results and briefing slides)

3. Demand Breakdown: Beyond GPUs and ASICs, CPUs Are the Third Layer

The Goldman Sachs analyst opened with the obvious question: is the SoC upgrade about GPUs, ASICs or CPUs? The answer is all three, but CPUs are the biggest factor.

Lefever was blunt: the industry did not foresee how much CPU demand agentic AI would create. Chief Customer Relations Officer Sanjeev Mohan added two mechanisms:

• Volume: agentic AI is driving very large server CPU shipments.

• Ratio: in inference, the ratio of CPUs to GPUs is rising.

On test time, Mohan conceded that CPUs are not as long as GPUs or custom ASICs, but they are far from short. Volume × meaningful test time × a rising ratio: multiply the three and CPUs become a clear tailwind for ATE (Automatic Test Equipment) results.

Another notable answer concerned x86 versus Arm. Lefever said Advantest serves both camps with the same V93000 tester, so it hardly matters who wins. The tester vendor is the arms supplier in this CPU architecture war, not a combatant, which also helps explain why its growth is outpacing peers.

4. Capacity Breakdown: 5,000 Units, 10,000 Units, and Next 20,000

Capacity was the main theme of the call. According to the slides, annual SoC tester capacity already exceeds 5,000 systems and the 10,000-unit target will be reached well ahead of schedule; the original plan was by the end of FY2028, with a firm date expected next quarter.

The final questioner from SMBC Nikko pushed further: what comes after 10,000? Lefever's answer: the next step is another doubling to 20,000, already under internal discussion based on customer demand, with timing possibly disclosed in the fourth Mid-Term Management Plan (MTP4) due in May.

The demand backing is solid. Responding to JPMorgan, management confirmed that both Q3 and Q4 were revised up, mainly because capacity is expanding faster than expected. Lefever added that, adjusted for currency, second-half revenue is up about 28% over the first half. In the guidance, the FY2026 SoC test system sales forecast rose from ¥1,243.5B in July to ¥1,375.0B, an increase of about ¥131.5B in one go.

This fits the back-end bottleneck we discussed in NVIDIA's CPO prepayments and the 15x capacity ramp, 2026 W43 Industry Review: the constraint on AI chips has moved from front-end wafers all the way to packaging and test, the "last mile".

5. CPO and Silicon Photonics: Long Test Times Are Both a Barrier and a Moat

The SBI Securities analyst noted that CPO (Co-Packaged Optics) needs test times as long as chiplets; otherwise yields suffer and whole packages may be scrapped. Lefever agreed: guaranteeing good yields on optical engines takes lengthy test time, which is a real tailwind for Advantest.

His sizing: the CPO-related ATE market should double or triple every year for the next few years, heading toward a billion-dollar market, and Advantest participates in every test insertion. But he was careful to add that, next to an SoC test market above $11B that is also growing at a 50%+ CAGR, CPO remains relatively small.

Mohan also touched on silicon photonics in another answer: Advantest's share in silicon photonics test is "very strong and growing".

The key insight here: CPO turns optical yield into an electronic test problem. A failed pluggable module can simply be swapped, but in CPO the optical engines are packaged with the switch chip, so one bad engine can sink an entire expensive package; testing has to move earlier and go deeper. For market forecasts on CPO volumes, see LightCounting's CPO and NPO forecast at OCP 2026.

6. Market Share: From 56% to 66%, Targeting Above 70%

The CLSA analyst asked about share. Lefever said SoC tester share rose from 56% in 2024 to 66% in 2025 and reiterated that there is "a path above 70%". He was explicit that 2026 is not flat but another year of share gains, continuing into 2027.

There are two sources of growth:

• Expansion at existing customers: accounts already using Advantest keep scaling volume at a high rate.

• Wins at new accounts: Lefever said Advantest can now take meaningful share at accounts where it was not the incumbent, because the HPC industry largely treats the V93000 as the standard.

A company representative then added a clarification: 70% is not an official commitment, and a formal statement will come at the end of FY2026 or the start of FY2027, that is, next April. "A path to" and "committed to" are two different levels of certainty; readers should keep them apart.

7. Management Outlook

FY2026 guidance (April 2026 to March 2027):

• Revenue: ¥1,863.0B (July forecast: ¥1,714.0B), up 65.1% YoY

• Operating income: ¥967.0B (July: ¥846.0B), 51.9% operating margin

• Net income: ¥741.5B (July: ¥660.0B)

• 2H revenue of ¥1,017.8B at a 50.1% operating margin

• 2H FX assumption of ¥150 per US dollar (1H actual: ¥160)

Market size (CY2026): the tester market forecast is unchanged at $13.0B to $14.5B, with SoC testers near the upper end of the $10.5B to $11.5B range and memory testers around the midpoint of $2.5B to $3.0B. Management expects the industry to remain supply constrained in CY2027, with end demand exceeding supply.

Longer term: Lefever said the ATE market has grown at about 50% or more a year for the last two years with no sign of slowing, and foundry partners expect a CAGR in the mid to high 50s for advanced nodes all the way through 2029. Formal CY2027 numbers will come with the Q3 call in January. This echoes the context in our 2026 W42 Industry Review on TSMC raising its growth outlook.

Reading the language:

• "High confidence" on pulling in 10,000 units: commitment level.

• "We believe the next step will be another doubling" on 20,000 units: a direction, not a plan, with no timeline.

• "See a path above 70%" on market share: confident but deliberately undated, and a company representative stepped in to temper it.

• Only "favorable" on CY2027 with no numbers: by convention quantified in January, so do not over-read it.

Shareholder returns were stepped up too: an interim dividend of ¥49 (last year's interim: ¥29) and a buyback of up to 11 million shares or ¥280B.

8. Risks: Costs, Currency and Memory

DDR costs. Both SoC and memory testers use a lot of DDR. The first half ran on inventory bought at old prices; from the second half Advantest faces higher DRAM spot prices like everyone else. Lefever said it will offset this with new configurations, licensing and new instruments, but dislikes direct price increases. This is one of the main reasons for the lower 2H operating margin.

One-offs fade. The first half included a one-time inventory reversal that management says will not recur, and operating margin should settle in the "low 50s".

Currency. The 2H forecast assumes ¥150 per dollar, while Q2 actually averaged ¥161. The company discloses that each ¥1 of yen depreciation against the dollar adds about ¥5.8B to FY2026 operating income. A persistently weak yen is upside; the reverse is a challenge to the forecast.

Memory shortage. UBS asked whether the memory shortage could block shipments. Lefever acknowledged memory is tight: wafer starts have shifted from legacy DRAM to HBM and server DRAM over the past two years, hurting industrial and automotive users, and Advantest is not immune. But customers understand that to get testers they have to supply the memory, as the industry did for each other during the 2021–2022 shortages. This is a supply chain bottleneck to track, not a demand problem.

9. Supply Chain and Customer Signals

• Terafab: an analyst raised the Terafab fab project. Lefever would not comment on specific customers but called it "very real", said it should lead to meaningful business, and sees a genuine global need for more SoC and memory capacity.

• Foundry partners: citing fabless customers and foundry partners, Lefever pointed to CAGRs in the mid to high 50s through 2029, the basis for multi-year test demand.

• Taiwan import data breaks down: Jefferies noted that the usual correlation between Taiwan equipment import data and SoC tester shipments failed this quarter. Lefever said models tracking Malaysian exports and Taiwanese imports are noisy and suggested other KPIs. A useful reminder for investors who forecast Advantest from customs data.

• Memory test: the FY2026 memory tester mix is expected at 85% DRAM and 15% non-volatile memory (last year 90% / 10%), and Q4 was flagged as "quite strong".

The spread of AI demand from GPUs to CPUs and networking is also visible in Celestica's Q3 FY2026 earnings call: the systems side is calling for $40B of revenue in 2027, and upstream test is the amplifier of the same capex wave.

10. Summary

Three metrics to track next quarter:

1. The firm date for 10,000 units of capacity: management says it will give it next quarter. The earlier the date, the higher the FY2027 revenue ceiling.

2. Whether 2H operating margin holds 50%: with DDR inflation and fading one-offs, this is where repricing through new configurations gets tested.

3. The CY2027 tester market size: quantified at the January Q3 call; watch whether the SoC test market sustains roughly 50% CAGR.

Testers are no longer the last equipment anyone thinks about in the semiconductor cycle; they are the meter that prices AI chip complexity.

With GPU, ASIC and CPU demand stacking up, and CPO turning optical yield into a test problem, Advantest faces only one question: can it build capacity fast enough?

This article is for technology and industry trend analysis only and does not constitute investment advice.