OCP Global Summit 2025 | Astera Labs | Trust at 64 GT/s: Security Considerations for PCIe 6 Switch Deployments

Introduction

As AI data centers and high-bandwidth computing expand rapidly, PCIe 6.0 has become a critical interconnect backbone. With speeds rising to 64 GT/s, lane counts exploding and connectivity stretching from the server to the whole rack and even across racks, security has become a design challenge that can't be ignored.

At OCP 2025, Astera Labs CTO Abdeshavia delivered a keynote — "Trust at 64 GT/s" — presenting a complete framework for securely deploying PCIe Gen6 switches. The talk wasn't just about cryptography; it explored how to build trusted data transport across multiple layers of connectivity (retimer, switch, root complex, endpoint).

Content

1. Background: Connection Density Is Reshaping Trust Boundaries

Abdeshavia opened by noting that computing architecture in the AI era has "moved beyond a single server to rack and multi-rack scale."

This means:

• More interconnect components (switches, retimers) are being introduced into the system;

• Data no longer flows only inside chips but crosses physical boundaries;

• As a result, every transport path becomes a potential attack surface.

Astera frames the challenge as: "How do we ensure data in motion keeps its confidentiality and integrity without sacrificing performance and latency?"

2. IDE: PCIe 6's Built-In Security Foundation

PCIe 6.0 introduces Integrity and Data Encryption (IDE) as a link-layer security mechanism.

IDE has two main phases:

1. Control Plane

   • The transmitter (TX) and receiver (RX) establish a secure session (Secure SVDM Session);

   • Symmetric keys are negotiated within the session for use in the data plane.

2. Data Plane

   • All TLPs (Transaction Layer Packets) are encrypted before transmission;

   • Packet headers stay in plaintext for routing;

   • The entire packet is wrapped in an integrity-protected envelope.

This means that even if untrusted intermediate devices sit in the path (such as third-party retimers or switches), data remains encrypted and protected against eavesdropping or tampering.

3. The Switch's Role and Security Challenges

Astera divides PCIe switch functions into two scenarios:

• Routing mode: the switch only forwards packets without modifying data;

• Conversion mode: the switch must perform protocol conversion (e.g., flit <-> TLP) and accesses plaintext data.

This leads to two different security models:

Mode	Security policy	Must the switch be trusted?	Latency/power impact
Selective IDE	End-to-end data encryption; the switch only forwards packets	No	Low
Link IDE	Each link segment is encrypted independently (the switch decrypts and re-encrypts)	Yes	High

Astera stresses that in conversion mode, the switch must be brought inside the trust boundary, because it has to decrypt data to complete the protocol conversion.

4. Attestation: Bringing the Switch Inside the Trust Boundary

In Link IDE mode, the switch must support an attestation flow to ensure its firmware, hardware and key management are all operating in a secure state.

The framework Astera uses includes:

• SPDM (Security Protocol and Data Model): for device-to-device authentication and key exchange;

• Secure Boot + Device Recovery: ensures the authenticity and integrity of the switch's boot firmware;

• Trusted Execution Domain (TDM): provides a secure enclave inside the switch to store keys and encryption logic.

Abdeshavia added: "The switch is no longer just a connectivity component but a secure node — it must pass verification before it can join the system's trust network."

5. Extending to Confidential Compute: TDISP and DSM

In data centers that support Confidential Computing (CC), the security challenge goes a step further.

Astera noted that in multi-tenant or virtualized environments, the switch must meet the following conditions:

• Support resource partitioning to prevent different tenants' data from interfering with each other;

• Include a built-in Device Security Manager (DSM) to ensure trusted devices are correctly brought into the trust domain;

• Comply with TDISP (TEE Device Interface Security Protocol) so devices can establish a secure channel with the CPU's Trusted Execution Environment (TEE).

In other words, PCIe switches will not only need to "move data" but also "understand the boundaries of security domains."

6. Trade-Offs in Performance, Power and Complexity

Astera was candid that security isn't free:

• Link IDE mode adds encryption/decryption latency (~hundreds of ns);

• Every port needs its own keys and security engine, increasing power and area;

• For a 64 GT/s switch with on the order of a hundred ports, this is a non-linearly growing challenge.

Astera's strategy, therefore, is to "choose the mode by application":

• For a single-tenant environment within a rack → Selective IDE is sufficient;

• For multi-tenant or rack-to-rack transport → Link IDE + Attestation + TDISP is required.

Conclusion

Astera Labs' talk lays out the reality of security design in the PCIe 6.0 era:

Connectivity is no longer just a physical-layer challenge but an extension of trust management.

From IDE and SPDM to DSM and TDISP, security protocols are permeating the entire interconnect stack.

Astera's "Scorpio Smart Switch" and "Aries Smart Retimer" put this strategy into practice, supporting all IDE modes with built-in security verification.

As data centers move from closed architectures to open standards (such as UALink, CXL and Ethernet fabrics),

this kind of security-layer design will become the foundation for "open interconnect you can trust."

Further Perspectives

1. Technical impact

   • Astera is treating "security" as a new functional dimension of the PCIe switch, not an optional add-on.

   • The combination of IDE + attestation establishes a unified trust framework for future CXL, UALink and PCIe interoperability.

2. Supply chain observations

   • Standardization of SPDM, TDISP and similar specs is driving the formation of a "secure semiconductor supply chain."

   • Astera's lead in retimer and switch security positions it to become the security gatekeeper of the CXL/PCIe ecosystem.

3. Market trends

   • As AI systems become more modular and virtualized, connection security will matter as much as performance.

   • Smart switches supporting IDE and attestation will become standard equipment in the next wave of PCIe 6 / CXL server architectures.