OCP Global Summit 2025 | UALink | Applications and Use Cases for UALink: Enabling Efficient, Open Networking for AI Scale-Up Systems

Introduction

At the 2025 OCP Global Summit, the UALink Consortium was one of the most closely watched open standards. The alliance, made up of companies including AMD, Intel, Broadcom, Cisco, HPE, Meta, Microsoft, Arista, Dell, Supermicro, Astera Labs and Synopsys, is trying to define a scale-up interconnect protocol for the AI era.

This expert panel, with participants from Astera Labs, Intel, Synopsys, Upscale AI and others, took a deep look at UALink's motivation, technical design, and collaboration with other open organizations such as OCP, UEC and the Ethernet Alliance.

In short, UALink represents the industry's consensus response to open GPU-to-GPU interconnect: it aims to break closed, proprietary architectures and give every vendor an interoperable, manufacturable and evolvable scale-up standard.

Content

1. Why do we need UALink?

A representative from Synopsys pointed out that as AI models keep growing, "the cluster is the new computer".

• Across past generations, the performance of a single GPU chip grew only about 2×;

• but when these GPUs are interconnected as a cluster (as in NVIDIA's NVL72 architecture), overall performance can increase by more than 30×.

This means the scale-up network itself has become the key to performance. Yet today's proprietary solutions (such as NVLink and Infinity Fabric) are each controlled by a single vendor and lack an open ecosystem.

UALink's goal is to establish a common language at this layer, letting any GPU, XPU or switch interconnect over a standard protocol.

2. Technical core: open, low-latency, energy-efficient

UALink uses the existing IEEE 802.3dj (200G/lane) physical layer and enhances packet efficiency and security features at the transport layer.

Its features include:

• Very high bandwidth efficiency: maximum throughput with minimal protocol overhead;

• Low-power architecture: designed around energy efficiency (power-aware networking);

• Confidential Compute support: security functions are built directly into the protocol layer rather than added as an extra layer.

Astera Labs noted that "optimizing bandwidth efficiency and power density" is the key to whether a scale-up network succeeds or fails:

if the network protocol itself is inefficient, it leads to extra switch ports, optical modules and copper cables, and wasted energy.

UALink is built around a "Bandwidth Efficiency First" philosophy, aiming for the best balance between performance and power.

3. Open standards and ecosystem strategy

Members of the UALink consortium stress that this is a "community-based, open collaboration model."

Similar to PCI-SIG, UALink will also launch:

• Integrator's List: all validated devices will be listed to ensure interoperability;

• Prototyping Platform: provided by Synopsys for multi-vendor FPGA emulation and Layer 3/4 testing;

• Interoperability Events: co-hosted with the Ethernet Alliance and OCP to encourage early chip-to-chip interop testing.

This operating model allows new technology to complete specification within one year, far faster than traditional standards bodies (PCIe takes about 3–4 years).

4. Timeline and deployment plan

• 2024 Q4: Synopsys has released UALink Controller and PHY IP;

• 2025 Q3–Q4: the first tape-out customers (chip design houses) are expected to complete samples;

• End of 2026: the first wave of UALink-capable GPUs and switches is expected to ship.

Upscale AI added that the top priority is to "build an interoperable multi-vendor ecosystem",

so that users can freely combine accelerators and switch chips from different brands and still achieve a high-speed scale-up fabric.

5. Collaboration with other standards

UALink does not exist in isolation.

It has technical exchanges with organizations including OCP, UEC, DMTF, the Ethernet Alliance and IEEE 802.3.

• OCP provides overall rack-level integration (power, cooling, system structure);

• UEC defines the Ethernet scale-up transport layer;

• DMTF and SONiC provide management and abstraction-layer support.

In other words, UALink focuses on Layer 1–3 scale-up interconnect,

complementing, rather than competing with, Ethernet-based scale-out networks.

6. Relationship with Ethernet / Ultra Ethernet (UEC)

An audience member specifically asked: "How is UALink different from Ethernet-based EON or Ultra Ethernet?"

The Intel representative explained clearly:

"Ethernet is still mainstream, but its packet overhead, latency and power are not ideal at the scale-up layer. UALink fundamentally optimizes on these dimensions."

The Broadcom representative added:

• Ultra Ethernet offers a new transport-protocol direction at Layer 4;

• UALink is a low-latency, purpose-built communication layer redesigned for Layers 1–3;

• the two can ultimately coexist, each applied at a different level of the GPU fabric.

This division of labor also hints that future data-center networks will adopt a layered interconnect architecture:

• CXL / PCIe: Chip-Level (Coherency)

• UALink: Rack-Level (Scale-Up)

• Ethernet / UEC / EON: Data Center-Level (Scale-Out / Across)

7. Industry vision: making the cluster the new computer

The panel's closing consensus:

"Rack will become the new unit of AI."

The future of AI isn't a single GPU, but an entire composable, scalable cluster.

UALink represents an open platform that every company can take part in,

bringing GPUs, FPGAs, memory, switches and NICs together under a unified protocol,

moving scale-up networking from closed to open, from proprietary to ecosystem.

Conclusion

The emergence of UALink is a concrete step toward opening up AI infrastructure.

It isn't just another interconnect technology but a shift in industry values:

from "single-vendor proprietary" to "multi-party co-creation," from "hardware competition" to "a collaborative ecosystem."

After 2026, as UALink-capable chips and switches roll out,

AI system designers will be able to freely choose suppliers on the same open protocol,

a structural release for the whole industry's cost, speed and capacity to innovate.

Further perspectives

1. Technical impact

   • UALink establishes a truly open Layer 1–3 standard for the "AI scale-up fabric."

   • It will become the bridge between CXL (memory coherency) and Ethernet (data-center networking),

     forming a three-tier architecture: CXL ↔ UALink ↔ Ethernet.

2. Supply-chain observations

   • Synopsys provides IP, Astera Labs focuses on retimers, and Broadcom and Intel lead on switch chips.

   • The consortium's collaboration structure maps almost the entire AI compute stack,

     meaning UALink has the potential to form an open GPU fabric ecosystem.

3. Market trends

   • The rise of UALink will challenge the dominance of closed architectures such as NVLink.

   • If the first implementations succeed in 2026, it could become one of the standard specifications for AI clusters,

     running in parallel with UEC/EON to form two major ecosystems: "open vs. proprietary."