OCP Global Summit 2025 | Avicena | Ultra-Low-Power MicroLED-Based Interconnects for AI Scale-Up Networks

Introduction

At OCP Global Summit 2025, Avicena Tech presented an interconnect innovation that departs from conventional silicon photonics (SiPh) and VCSELs: MicroLED-based optical interconnects.

Their argument is clear: "wide and slow" is the best answer for interconnect inside future AI systems, rather than chasing "fast and narrow."

Avicena's MicroLED architecture is defined by ultra-low power, short reach and high density, making it especially suited to AI scale-up networks, the "internal optical interconnect" between GPUs, memory and accelerators.

Content

1. Background: The Energy Dilemma of the AI Era

Avicena opened by noting that with the explosive growth of large language models (LLMs) and GPU clusters, interconnect power is rapidly consuming a large share of global energy use.

Compute growth (especially in GPU clusters) has long outpaced the growth curve of interconnect bandwidth, making network power the bottleneck of AI infrastructure.

Next-generation interconnects must therefore treat "energy efficiency" as the first design principle.

2. The Concept: Replacing Lasers with MicroLEDs

At the core of Avicena's technology is applying "display-grade" MicroLED arrays to data transmission.

The basic concept is as follows:

• The transmitter (TX) carries hundreds of GaN MicroLEDs (about 50 µm pitch each),

• mapped to a photodetector array at the receiver (RX) via a multicore fiber bundle.

  It is like docking a "MicroLED display panel" to a "CMOS image sensor," forming a wide-channel, low-rate, high-density optical link.

This design avoids the complex packaging of lasers and modulators, enabling multichannel transmission at lower cost and higher reliability.

3. Results and Performance Metrics

Avicena has already shown concrete results:

• The first-generation chip achieves 4 Gbps per channel,

• A GaN MicroLED prototype has reached 16 Gbps in the lab.

  Per-channel speed is modest, but with hundreds of LEDs running in parallel, aggregate bandwidth reaches several Tb/s.

More importantly, its energy efficiency:

• Under 1 pJ/bit (die-to-die mode),

• still <1.5 pJ/bit including high-speed drivers,

• Reach of 10–20 meters, with some tests exceeding 30 meters.

This places MicroLED optical interconnect between copper (short reach) and silicon photonics (long reach), forming a new "mid-reach optical layer."

4. MicroLED Optical Interconnect vs. Conventional SiPh / VCSEL

In the Q&A, Avicena clearly compared MicroLED with existing technologies:

Technology	Per-channel rate	Cost	Efficiency (pJ/bit)	Manufacturing maturity	Notes
VCSEL	32–50 Gbps	High	5–10	Mature	Fast but costly, with limited lifetime
SiPh (EML)	100 Gbps+	Very high	4–6	Complex	Suited to long reach but power-hungry
MicroLED	4–16 Gbps	Low	<1.5	Volume-ready (GaN ecosystem)	Wide & slow, low power, high reliability

Avicena does not see MicroLED as competing with SiPh or VCSELs; instead it targets "internal optical interconnect for scale-up" as a key gap-filler replacing copper and short-reach laser modules.

5. Architecture and Applications: Die-to-Die and Mid-Reach Optical Interconnect

The ideal use cases for this technology include:

• Die-to-die / chip-to-chip interconnects (e.g., UCIe, CXL)

• Intra-rack GPU/memory fabric

• Active optical cables (AOC) and onboard optics

Avicena's design supports:

• Direct integration with high-speed SerDes chips (co-packaged on a CMOS platform)

• Multiple packaging levels (board, module or package level)

• 
  Co-development with TSMC of a high-sensitivity APD CMOS receiver, sharply reducing receiver power and noise.

These modular building blocks let MicroLED interconnect scale quickly across AI compute architectures, especially for GPU memory fabrics and extended HBM interconnect.

6. Power, Density and Thermal Characteristics

Avicena emphasized three design dimensions:

• Efficiency: Measured 0.22 pJ/bit (Tx-only), with total power 10x lower than comparable optical modules.

• Density: >2 Tbps/mm shoreline density, with bandwidth scaling out through 2D arrays.

• Thermal stability: GaN MicroLEDs operate from –55°C to 125°C, and have even been shown emitting light at 400°C.

  This extreme thermal stability makes them especially suitable for placement right next to GPUs or ASICs (i.e., co-packaged or on-package environments).

7. Manufacturing and Reliability

On manufacturing, Avicena leverages existing MicroLED display production lines (the same technology used in automotive headlights and displays), giving it mature yields and a foundation for high-volume production.

Its partners include:

• OSRAM (automotive-grade LED packaging and assembly/test know-how)

• TSMC (integrating the CMOS receiver and packaging flow)

Lifetime testing has accumulated more than 10,000 hours with consistent brightness and transmission stability, indicating long-term reliability far above laser-based devices.

Conclusion

Avicena's MicroLED optical interconnect offers a way of thinking that differs from the mainstream:

"Make light simpler, wider and more energy-efficient."

In AI data centers, the tension between bandwidth and power at the scale-up layer is growing ever sharper.

With ultra-low power, high reliability and manufacturability,

MicroLED could become a next-generation optical option for GPU/memory fabrics and chiplet interconnect.

The core significance of this technology:

• It redefines optical interconnect as no longer synonymous with high-end, expensive and complex.

• It brings light into the chip, making it a link medium on equal footing with electrical signals.

Further Perspectives

1. Technology impact

   • Avicena's "wide and slow" strategy marks a turning point for power in AI system interconnect.

   • It clearly complements silicon photonics (SiPh): SiPh addresses scale-out (long-reach, high-speed), while MicroLED focuses on scale-up (short-reach, high-density).

2. Supply chain observations

   • Avicena has successfully combined GaN processes with CMOS photodetection, opening a non-traditional optoelectronic integration supply chain.

   • If the technology matures, the combination of OSRAM + TSMC + Avicena could challenge the position of existing optical module makers and SiPh packaging houses.

3. Market trends

   • This technology is especially well suited to future AI accelerator disaggregation architectures,

     for example replacing PCB routing between GPUs, HBM and NICs with low-power optical links.

   • In the long run, MicroLED interconnect could become a standard element of "optoelectronic integrated circuit (OEIC) design,"

     bringing light all the way from external modules into the package.