OCP 2025 APAC Summit: UALink Overview

UALink 1.0: An Open Scale-Up High-Speed Interconnect for AI and HPC — OCP 2025 APAC Summit

At OCP 2025 APAC Summit, UALink Consortium chair Curtis Bowman gave a deep dive into the UALink 1.0 specification, an open scale-up fabric designed for AI and HPC (high-performance computing) workloads. As AI models and datasets explode in size, the memory of a single GPU is no longer enough; UALink offers a way to combine many accelerators into one large virtual accelerator. It is low-latency, high-bandwidth and low-power, and built on a fully open standard that lets any CPU, GPU, accelerator or switch join, avoiding single-vendor lock-in.

Key Points

1. Why UALink Is Needed

• Exploding AI memory demand: the parameters and datasets of large AI models exceed the memory of a single GPU, so multiple GPUs/accelerators must work together over an efficient interconnect.

• Existing options fall short: standards such as PCIe and CXL cannot meet the latency and bandwidth requirements; NVLink, today's de facto market standard, is proprietary to NVIDIA, and its closed nature limits industry innovation.

• Goal: establish a high-performance, scalable and fully open scale-up interconnect standard.

2. Architecture and Technical Features

• Open protocol

  • Any CPU, any accelerator and any switch can participate.

  • UALink defines its own protocol, transaction and data link layers, while the layer below uses the IEEE 802.3dj 200G PHY, fully compatible with existing cables, connectors and retimers.

• Scalability

  • Supports 8–1,000 accelerators (interconnected over copper).

  • Provides virtual pods so resources can be partitioned among different tenants.

• High performance and low latency

  • 200 Gbps per lane, up to 800 Gbps per link.

  • After protocol optimization, latency is only 210–260 ns, far below Ethernet's 650 ns–1.3 μs.

  • Memory channels and packets are efficiently interleaved, allowing requests and responses for multiple targets to travel in the same packet.

  • Bandwidth efficiency reaches 93% (Ethernet is about 65–90%).

• Power and area advantages

  • Per-port logic area is only 1.5 mm² (Ethernet is about 10 mm²).

  • Lowers switch and accelerator power, improving overall system energy efficiency.

• Feature extensions

  • Supports in-network collectives, offloading part of the computation to the network layer.

  • Plans for UALink chiplets so vendors can integrate I/O capability quickly.

3. Ecosystem and Roadmap

• Industry support: more than 100 members, including chip designers, cloud service providers, ODMs and IP providers (such as AWS and Apple).

• Technical heritage: based on AMD Infinity Fabric, optimized with technical input from members.

• Future versions:

  • Support for the 128G PCIe PHY is coming.

  • In-network compute features and switch support will be added, with samples as early as the beginning of next year.

  • A compliance certification program will ensure interoperability across multi-vendor implementations.

4. Comparison with NVIDIA NVLink Fusion

• NVLink Fusion: requires NVIDIA CPUs/GPUs and NVIDIA switches; it is highly closed, and outside vendors cannot influence its direction.

• UALink: fully open, interoperable across vendors, and lets the community jointly decide how features evolve.

Conclusion

The launch of UALink 1.0 gives AI and HPC an interconnect path that escapes single-vendor lock-in while meeting high-bandwidth, low-latency and scalability needs. Building on existing Ethernet and high-speed interconnect technologies, and deeply optimized for load/store operations between accelerators, it delivers performance well beyond today's open standards. As faster PHYs, in-network compute and chiplet integration land, UALink is well positioned to become the industry standard for the open scale-up fabric.