2025 OCP APAC Summit | Advanced CPO Integrated by CoWoS and COUPE | TSMC

Summary

At a recent technology forum on high-performance computing (HPC) and AI systems, TSMC unveiled breakthroughs in advanced Co-Packaged Optics (CPO) technology. Through heterogeneous integration of CoWoS/COAS and COUPE (Compact and Universal Photonic Engine), it delivers optical I/O with lower energy consumption (2–5 pJ/bit) and higher bandwidth. The technology supports both Grating Coupler (GC) and Edge Coupler (EC) architectures and takes heterogeneous die stacking, 3D integration and optical packaging to a new level, laying critical groundwork for future CPO and AI supercomputing.

Content

1. Background and Motivation

As compute demand in AI and HPC systems explodes, traditional Moore's Law can no longer keep up with the extreme requirements for bandwidth and power. Heterogeneous integration has become a new path to system performance, and CPO (Co-Packaged Optics) is seen as the core architecture of the next generation.

TSMC's strategy is to combine its CoWoS platform with the COUPE photonic engine, packaging the compute module and the photonic engine in the same module to break through the energy-efficiency and bandwidth bottlenecks of today's pluggable optics.

2. CoWoS Technology Evolution and Variants

The CoWoS platform is the core of 2.5D/3D integration and comes in three variants:

• CoWoS-S: large monolithic silicon interposer

• CoWoS-R: organic interposer

• CoWoS-L: composite interposer

  Its signature feature is the LSI interposer, which extends heterogeneous integration to the interposer level for optimal system performance.

A look back at TSMC's technology roadmap:

• 2016: HBM integration begins

• 2020: maximum interposer size reached

• 2024: CoWoS-L development completed

  Going forward, TSMC will keep pushing toward larger sizes, higher density and more complex 3D structures.

3. COUPE Photonic Engine Architecture

COUPE (Compact and Universal Photonic Engine) uses SoIC stacking (EIC on PIC) and has the following key features:

• Compatible with both GC and EC: the GC architecture is developed first because its supply chain is more mature

• SOI handle removed: reduces optical-path insertion loss, achieving a low 1.2 dB loss

• Backside metal reflector + silicon-aligned beam: optimizes the vertical optical path, reducing reflection and dispersion

• AR coating and optimized process: ensures a 1 dB bandwidth of 25 nm with a peak wavelength shift of 1.7 nm

4. Performance and Energy-Efficiency Breakthroughs

Through CoWoS + COUPE integration:

• Energy efficiency:

  • OE on substrate: about 5 pJ/bit

  • OE on interposer: about 2 pJ/bit

  • Conventional pluggable optics: about 10 pJ/bit

• Bandwidth scaling strategy:

  1. Faster PIC/EIC speeds

  2. Shorter distances through package structure (tighter coupling of the compute module and COUPE)

  3. More fiber channels

5. Supply Chain and Industry Challenges

Bringing CPO to large-scale commercial use requires supply chain innovation and collaboration, including:

• CP/FD test technology

• FAU (Fiber Array Unit) innovation

• High-yield optical packaging and high-speed assembly processes

These challenges require collaboration across materials, packaging, testing and system design to deliver solutions that combine low power with high bandwidth.

Conclusion

Through the integration of CoWoS and the COUPE photonic engine, TSMC has presented a clear CPO technology roadmap aimed at meeting AI and HPC's extreme bandwidth and low-power requirements. The core advantages of this technology include:

• Energy consumption below 5 pJ/bit

• A universal design supporting both GC and EC

• Scalability through 2.5D/3D heterogeneous integration

• Long-term competitive advantage driven by supply chain collaboration

Going forward, as interposers and optical engines move into volume production, CPO will gradually replace pluggable optics in some high-end applications and become indispensable infrastructure for AI supercomputing systems.