Google's eighth-generation TPU splits into two architectures for the first time. STT breaks down how TPU 8t removes the training I/O bottleneck, and how TPU 8i uses large on-chip SRAM and OCS optical circuit switching to cut MoE inference network hops by 56%.

AMD's OCP keynote was framed around open standards, but the line worth underlining is the CPU-to-GPU ratio converging from 1:4 toward 1:1. Agentic workflows hand orchestration, retrieval and tool execution back to the CPU — and that matters far more to Taiwan's rack-integration and scale-up optical interconnect supply chain than a slide full of open acronyms.