CPO at a Turning Point: How Can the Supply Chain Close the Last Mile to Volume? (OFC 2025)

🔷 Introduction | Co-Packaged Optics: The Moment It Moves from Lab to Volume

As AI drives an explosion in data center bandwidth, Co-Packaged Optics (CPO) is seen as the next-generation high-speed interconnect after pluggable optics. By integrating the optical engine and the switch ASIC tightly in the same package, CPO not only cuts power and latency but also breaks through the physical limits of conventional modules.

Yet the gap between technical feasibility and volume production is substantial. Packaging, lasers, test and design tools all still carry unresolved problems. This article summarizes the views shared at an OFC Workshop by technical leaders from NVIDIA, Broadcom, Intel, Marvell and others on CPO manufacturability and industry progress, organized around seven core questions that capture today's real challenges and where innovation is heading.

❶ How can CPO scale to high-volume manufacturing? (e.g., cost)

• Tom Gray (NVIDIA)

  • The cost structure depends on large GPU shipment volumes driven by AI/ML applications.

  • In scale-up (in-rack) links, CPO has to compete with low-cost copper.

• Anand Ramaswamy (Broadcom)

  • Fully automated packaging and test flows are the key to controlling cost and reaching volume.

• Nicholas Psaila (Intel)

  • Test time must shrink from minutes to seconds to support large-scale production.

  • Low-cost materials and passive connectors are a must.

• Antonio Tartaglia (Ericsson)

  • Prototyping and volume production should use the same equipment and processes to save time and cost.

  • Standardizing the system architecture will reduce complexity and overall cost.

• Bardia Pezeshki (Avicena)

  • MicroLED technology can directly leverage existing display manufacturing, sharply reducing cost.

❷ What key technical and integration challenges must CPO overcome?

• Tom Gray (NVIDIA)

  • The key challenges include packaging, stacking, laser integration and thermal management.

  • Testability after system integration is another barrier to volume production.

• Matt Traverso (Marvell)

  • Maintaining signal integrity in linear systems and cross-platform compatibility are the core technical challenges.

• Nicholas Psaila (Intel)

  • Throughput and consistency must be considered across test, rework and integration.

• Robert Lee (Corning)

  • High-precision integration and reliability at the fiber-to-chip interface need to be solved.

• Antonio Tartaglia (Ericsson)

  • A fragmented supply chain and design that is out of sync with manufacturing are today's bottlenecks.

❸ What packaging innovations are needed? (e.g., fiber connectors, TSV, interposers)

• Anand Ramaswamy (Broadcom)

  • Use detachable fiber connectors to improve modularity and yield.

• Pooya Tadayon (Ayar Labs)

  • Push passive alignment, modular stacked designs and testable contact points.

• Hiroyuki Mieno (AGC)

  • Develop an optical redistribution layer (Optical RDL) to avoid attaching fiber directly to the chip.

  • Use polymer waveguides embedded in the substrate for coupling.

• Robert Lee (Corning)

  • Develop ion-exchange glass technology and multi-fiber barrel-type connector interfaces.

• Akihiro Noriki (AIST)

  • Develop high-density waveguide arrays with a pitch of only 20μm to raise bandwidth density.

❹ How mature are external and embedded laser solutions?

• Tom Gray (NVIDIA)

  • Because of thermal and integration requirements, external lasers are currently preferred.

• Antonio Tartaglia (Ericsson)

  • Approaches vary by vendor; laser integration still lacks clear standards and maturity.

❺ How can design for manufacturability be strengthened? (e.g., ADKs)

• Sander Roosendaal (Synopsys)

  • Design flows must support integrated electrical, thermal and optical co-design and simulation.

  • PDKs/ADKs need to be standardized and include DRC capability.

• Antonio Tartaglia (Ericsson)

  • Volume production must be considered from the earliest design stage, using consistent tools and processes.

❻ As systems scale, how can thermal effects be managed effectively?

• Tom Gray (NVIDIA)

  • Thermal management when CPO is co-located with 1–2kW-class GPUs is a core challenge.

• Sander Roosendaal (Synopsys)

  • Thermal simulation and design are needed at both the chip and package level.

❼ What actions would make the CPO ecosystem healthy and scalable?

• Pooya Tadayon (Ayar Labs)

  • Optical processes should align with electronic packaging flows to drive standardization.

• Nicholas Psaila (Intel)

  • Build IC-style ATE test platforms.

  • Reduce adhesive cure times and simplify fiber attach designs.

• Robert Lee (Corning)

  • Co-develop new glass-based connectivity solutions with industry partners.

🔷 Conclusion | From Prototype to Volume: Industry Collaboration and Standardization Are What Matter

Getting CPO to volume is no longer about a single company solving a technical problem; it requires the whole supply chain and design toolchain to evolve together. From package structure to fiber connectors, from laser sources to test flows, without common platforms and process standards, cost and yield at volume will remain the gating factors.

Fortunately, many vendors have already begun collaborating and experimenting on these issues: detachable fiber interfaces, optical redistribution layers (RDL), high-throughput test equipment and integrated design kits (ADK/PDK) are all taking shape. If the industry can converge on fuller consensus and standardized flows over the next few years, widespread CPO adoption will not be far off.