OCP Global Summit 2025 | Astera Labs | Beyond the Spec: What It Takes to Deploy UALink at Rack Scale
Introduction
At this year's OCP Global Summit, Astera Labs delivered a highly strategic talk: how to deploy UALink at the actual rack level.
The talk went beyond protocol and silicon developments to focus on end-to-end practice: “IP → silicon → boards → rack → software management → security → interoperability validation.”
For Astera, UALink isn't just a specification but a complete open scale-up ecosystem architecture.
As they put it: “For UALink to succeed, you need more than a standard — you need systems that can run in real data centers.”
Content
1. An Open Protocol Is Only the Starting Point: The Scale-Up Challenge
Ahmad Desh, product director at Astera Labs, said:
“To build a truly open, deployable scale-up network, a specification alone isn't enough. We need to connect everything step by step, from protocol to hardware to software.”
He summarized five essentials for deploying UALink successfully:
A TCO- and performance-optimized protocol: balancing performance, reliability and energy efficiency.
Scalability from component to rack: ensuring designs span chips, modules, switches and full racks.
Manageability & Telemetry: rack-level monitoring and dynamic configuration.
Reliability and security (RAZ & Data Privacy): ensuring isolation and recoverability in multi-tenant environments.
Ecosystem interoperability and deployment validation: making chips and platforms from different vendors truly interoperate.
2. The Evolution and Goals of UALink
Since the UALink Consortium was formed in late 2023, Astera has been one of its driving members.
In just one year:
The UALink 1.0 specification has been completed, providing a high-bandwidth, low-latency, energy-efficient transport layer;
A next-generation specification is under development that will introduce In-Network Compute to improve performance-per-watt.
Astera said: “UALink is a protocol born for scale-up — not just an extension of PCIe or Ethernet.”
It is designed to replace proprietary interconnects (such as NVLink and Infinity Fabric) as the open foundation between GPUs, XPUs and switches.
3. From Chip to Rack: The UALink Deployment Architecture
Astera presented a clear Rack-Level Deployment Blueprint with three core layers:
(1) Pod Controller
Located at the top of the rack or in a virtualized node, responsible for:
Automatically discovering all UALink components (XPUs, switches)
Assigning device IDs and creating virtual clusters (vPods)
Managing connection topology and resource isolation
It can be integrated into existing rack management frameworks such as OCP OAI, OpenBMC or SONiC.
(2) Node Management Agent
Runs at the BMC layer of the XPU/GPU,
handling node initialization, vPod joining and security isolation.
(3) Switch Management Agent
Runs on the scale-up switch and can be embedded in a KAMI module or an open NOS (such as SONiC).
It communicates via SAI (Switch Abstraction Interface) and UALink extension modules.
Together, these three form UALink's Distributed Control Plane, allowing each rack to be automatically discovered, configured and managed.
4. Reliability and RAZ (Reliability, Availability, Serviceability)
Astera noted that in AI clusters, any link interruption can trigger hours of training restarts, so RAZ is the top priority.
UALink builds in the following mechanisms:
Link-Level CRC and Flow Control: real-time error detection and retransmission.
Link Retry & Drop Modes: automatically isolating a link when it misbehaves to prevent errors from spreading.
Error Injection Framework: supporting error-injection testing and exception simulation.
Event Notification Hooks: reporting to the Pod Controller in real time for reconfiguration.
These mechanisms give the scale-up network a “self-healing” capability.
5. Security and Multi-Tenant Design
Astera also highlighted the security model of virtual clusters (vPods).
In multi-tenant cloud environments, different tenants may share the same rack.
UALink provides:
End-to-end encryption (AES-GCM): encryption is initiated by the XPU and stays encrypted across the entire fabric.
Integrity Tag (Authentication Tag): ensuring packets aren't tampered with in transit.
Isolation Mode: automatically isolating a link when anomalies are detected, without disrupting the overall network.
These security mechanisms allow UALink to be deployed safely in public cloud data centers.
6. Interoperability and Validation Program
Astera stressed that a truly open protocol must interoperate across chips.
To that end, the UALink Consortium has launched three-stage validation:
IP-level simulation: cross-company FPGA validation (Synopsys, Astera, Intel).
Pre-silicon interop testing: using emulation platforms to confirm protocol compliance.
Compliance Program (launching in 2026):
Any XPU must interoperate with any switch;
A public Integrator’s List will be established to ensure interchangeability.
Astera said: “This is the most important step to guarantee openness — not just writing a spec, but actually proving it works.”
Conclusion
Astera Labs' talk at OCP 2025 made it clear that UALink is moving from paper specification to real deployment.
What they are building is not just a protocol but a complete ecosystem that any vendor can join and that can run in cloud environments.
The value of “open” lies in being deployable, not in being debatable.
Through coordinated development of silicon, boards, software and test standards,
Astera is turning UALink from a “spec” into a working Rack-Level Infrastructure Blueprint.
Further Perspectives
Technical implications
Astera plays the role of “ecosystem integrator,” with a presence spanning retimers, switches and the software stack.
Their design philosophy — consistent deployability from hardware to software — will be key to an open AI fabric.
Supply chain observations
The UALink Consortium, built jointly by Astera, Synopsys, Intel, Broadcom, AMD and others, is forming a complete value chain to counter proprietary architectures (such as NVLink).
This will open new “composable” architecture opportunities for server makers (such as Supermicro, Dell and HPE).
Market trends
If UALink achieves cross-vendor interoperability and volume production in 2026, it will reshape the AI scale-up networking ecosystem.
At that point, the data center interconnect layer may split into three standardized tiers:
CXL: Chip-Level Coherency
UALink: Rack-Level Fabric
Ethernet / UEC: Scale-Out & Data Center Networking
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