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VLSI 2026 | Paper Analysis | Marvell Pushes a 3nm FinFET 212.5Gbps SerDes to 55dB Reach and 2.05pJ/bit: The Longest-Reach, Most Efficient Yet
Marvell's 3nm FinFET 212.5Gbps SerDes hits 54.7dB reach and 2.05pJ/bit, the longest-reach and most efficient published at this rate. A shared PLL plus heavy DSP equalization breaks the old rule that reach costs power, giving 1.6T racks structurally more room in cable length and power budget.
2 days ago


VLSI 2026 | Paper Analysis | University of Washington Pushes a Single Wavelength to 320Gb/s: Coherent QAM with MRMs Beats PAM-4 at 0.69pJ/b
Instead of piling on more laser wavelengths, the University of Washington uses microring modulators for coherent QAM, pushing a single wavelength to 320Gb/s at just 0.69pJ/b. RAMZI sidesteps MRM amplitude-phase coupling and time-multiplexed thermal tuning cuts the cost of thermal stability, delivering coherent, low-power and compact on low-cost 45nm silicon photonics.
2 days ago


VLSI 2026 | Paper Analysis | NTT Uses a Membrane to Shrink a III-V Modulator to 26fF: 67GHz+ 3-dB Bandwidth and 0.75pJ/bit for Short-Reach Optical Interconnects
NTT cut the junction capacitance of a III-V electro-absorption modulator to 26fF with a membrane structure, pushing device bandwidth past 67GHz at just 0.75 pJ/bit system energy. We walk through all 11 figures of this VLSI 2026 paper.
2 days ago


VLSI 2026 | Paper Analysis | NVIDIA Uses a "Self-Timed DFE" to Push Optical Receiver Sensitivity to -18.5 dBm at 0.416 pJ/b
NVIDIA's 32 Gb/s optical receiver reaches -18.5 dBm sensitivity at 0.416 pJ/b with an almost free trick: reusing the rail-to-rail TIA output as a noise-free DFE decision, trading under 1 mA for 2 dB of sensitivity. Why receiver sensitivity is the best investment in the whole optical link — explained figure by figure.
2 days ago


VLSI 2026 | Technical Paper Analysis | NVIDIA Squeezes -17.3dBm Sensitivity Out of a Differential TIA: A Counterintuitive Design for Direct-Detection Optical Receivers
Direct-detection optical receivers normally use only one terminal of the PD. NVIDIA recovers the wasted cathode current to build a differential TIA, improving sensitivity by roughly √2. The TIA doubles, but laser power across the whole link drops. A figure-by-figure walkthrough of VLSI 2026 C20.2.
2 days ago


VLSI 2026 | Technical Analysis | When Packaging Becomes AI's Main Battleground: Decoding TSMC's 3.5D System Integration Blueprint (Figures 1–19 Walkthrough)
AI's performance bottleneck is no longer compute but data movement across chips and packages. At VLSI 2026, TSMC answered with its 3DFabric platform: make the package itself the vehicle for AI scaling. We walk through all 19 figures, from 48x compute and 34x HBM bandwidth to power-thermal co-optimization and agentic EDA.
2 days ago
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