VLSI 2026 | Paper Analysis | NTT Uses a Membrane to Shrink a III-V Modulator to 26fF: 67GHz+ 3-dB Bandwidth and 0.75pJ/bit for Short-Reach Optical Interconnects
NTT has integrated a membrane III-V electro-absorption modulator (EAM) with a distributed feedback (DFB) laser on a silicon photonics platform. The membrane structure cuts junction capacitance to 26fF, pushing the device's own 3-dB electro-optic bandwidth past 67GHz. The standalone device runs 150-Gbit/s NRZ; once a CMOS driver is "embedded in the substrate" right next to the optics to form an optical chiplet, it delivers measured 64-Gbit/s PAM4 at just 0.75 pJ/bit. The value of this paper isn't "yet another modulator" — it tackles the two biggest pain points of short-reach optical interconnects at once, high bandwidth and low power, and it does so through material structure (the membrane) rather than by throwing a more expensive driver at the problem.
1. Background: NTT's Full "Membrane Optical Engine" Stack at VLSI 2026
First, who wrote this and where. The authors are Shinji Matsuo et al. of NTT (Device Technology Labs and Device Innovation Center), presented at the 2026 IEEE Symposium on VLSI Technology and Circuits. Shinji Matsuo has worked on membrane lasers for more than a decade, and this paper is essentially NTT's summary of how its accumulated membrane-laser technology converges on the most practical battleground: short-reach optical interconnects inside the data center. AI and high-performance computing (HPC) have pushed intra-data-center interconnect into an awkward spot: bandwidth density must go up and energy per bit must go down, both at the same time. Silicon photonics has become the mainstream platform thanks to process uniformity and scalability, but silicon doesn't emit light and its electro-optic efficiency is weak, so the industry has long sought to integrate high-efficiency III-V compound semiconductor modulators onto it.
2. The Core Problem: What NTT Is Solving, in One Sentence
Conventional high-mesa III-V EAMs integrated on silicon have too much junction capacitance, which caps electro-optic bandwidth and drags driver power up with it; NTT's answer is to build the III-V as a "membrane", using a geometrically thinner junction to cut capacitance from about 100fF to 26fF and loosen both the bandwidth and power bottlenecks at once. The problem isn't that the laser isn't bright enough, nor silicon waveguide loss, nor a poor choice of modulation principle (EAMs are already a good fit for short reach). The real bottleneck is that parasitic junction capacitance. Large capacitance means a large RC time constant, which eats high-frequency signal; to push the signal through, the driver has to source more current, and power blows up. The membrane structure goes straight after that capacitance.
3. Device Structure: How the EA-DFB Laser Sits on the Silicon Waveguide (Figure 1)
This figure shows how the whole membrane EA-DFB laser sits on the silicon photonics platform, and the cross-section design of the laser and modulator sections. Fig. 1(a) is the overall schematic — a membrane device integrating the EAM and DFB laser on a single silicon waveguide. Fig. 1(b) is the cross-section of the DFB laser section: the active region is buried in an InP layer and uses a lateral p-i-n junction, so the optical field forms a supermode with the underlying silicon waveguide. Fig. 1(c) is the cross-section of the EAM section. Here NTT deliberately removes the silicon waveguide to raise the optical confinement factor in the active region and make modulation more efficient. The lateral p-i-n junction is the structural basis for the membrane device's low capacitance.
4. Device Performance: 67GHz Bandwidth and a 150-Gbit/s Eye (Figure 2)
This figure shows the EO response of the EAM with a 150-µm active region, plus a 150-Gbit/s NRZ eye diagram — direct proof of the membrane structure's speed. This is the paper's headline device-level result. The single EAM's measured 3-dB EO bandwidth exceeds 67GHz, the bandwidth dividend paid out directly by the lower junction capacitance. Active region 150µm, 3-dB EO bandwidth >67GHz, and a clearly open 150-Gbit/s NRZ eye, measured at a laser bias current of 57mA and EA bias of 1.0V. The 67GHz figure puts the membrane EAM on the same starting line as state-of-the-art modulators, and it was earned by structurally lowering capacitance.
5. Packaging Architecture: An Optical Chiplet with the Driver Embedded in the Substrate (Figure 3)
This figure shows NTT's optical chiplet architecture — a device-embedded substrate that brings the electronic IC (EIC) and photonic IC (PIC) extremely close together. The EIC is embedded face-up between upper and lower substrates, while the EAM-bearing PIC is mounted face-down on the upper substrate. The two are electrically connected through vias in the substrate, with Cu-ball bonding for power and RF signals. The key is minimizing the EIC-PIC electrical interconnect: shorter interconnects mean smaller parasitics, which is the other half of the answer for low power and high frequency (the first half being the membrane's low capacitance).
6. Four-Channel PIC: 1×4 Splitter and Spot-Size Converter (Figure 4)
This figure shows the photonic chip itself — a four-channel EAM array integrated on silicon waveguides, and how light is split and coupled to fiber. Input light is divided four ways by a 1×4 splitter to feed the four-channel EAM array. Fiber coupling uses a spot-size converter made of a silicon taper plus a SiOₓ core waveguide, transforming the small on-chip mode into a large mode suited to fiber. This is the component that determines packaging yield and coupling loss. A 1×4 split feeding a four-channel array is the standard way to replicate single-channel capability into parallel bandwidth density.
7. The Prototype: Dual PICs and Fiber Arrays on Board (Figures 5 and 6)
These two figures show the architecture built as real hardware — top and cross-section photos of the prototype optical chiplet on its evaluation board. Fig. 5 is a top view: two PICs and two fiber arrays assembled together on the driver-embedded substrate, proving multi-channel optical chiplet integration can actually be built. Fig. 6 is a cross-section of the same chiplet, showing how the upper and lower substrates, embedded EIC, and face-down PIC stack up in physical form. These photos mark the leap from schematic to measurable hardware — evidence of manufacturability.
8. Driver Design: Three Inverter Stages and Dual Supplies to Save Power (Figure 7)
This figure shows the CMOS differential driver used for the EAM. Fig. 7 is a differential driver built from three inverter-type amplifier stages. Because the EAM needs a reverse bias of about 1V, the authors add a bias circuit on the EAM's n-side. The bias circuit and amplifier run on separate supply voltages: the bias circuit operates at a higher supply voltage, while the amplifier needs a lower voltage but more current. Splitting the two supplies lowers overall power — one of the circuit-level techniques behind the 0.75 pJ/bit figure. This "separate rails for bias and amplification" approach is a useful reference for module makers chasing pJ/bit.
9. Capacitance Is the Star: 26fF vs. 100fF Bandwidth Showdown (Figure 8)
This figure shows the measured EO response of the full optical chiplet and uses two simulated curves to quantify the membrane structure's capacitance advantage. Fig. 8 compares measurement with simulation. The whole chiplet's measured 3-dB EO bandwidth is about 18GHz, matching a simulation that assumes a membrane EAM junction capacitance of 26fF. For comparison, swapping in 100fF — representative of a conventional high-mesa III-V EAM — drops simulated bandwidth to just 12GHz. 26fF vs. 100fF, 18GHz vs. 12GHz: the figure proves in the plainest way that lowering junction capacitance with the membrane structure buys bandwidth directly. (Note that 18GHz here is the system bandwidth of the whole chiplet including packaging and driver — a different level of measurement from the >67GHz bare device in Figure 2.)
10. Test Platform: Four-Channel Measurement at 1320nm and 13dBm (Figure 9)
This figure shows the full measurement setup used to validate the optical chiplet. Fig. 9 is the setup. Laser CW power is set to 13dBm feeding the four-channel EAM array, at a wavelength of 1320nm in the O-band. The output is captured by a photodiode (PD) plus transimpedance amplifier (TIA). Laser at 13dBm, 1320nm, PD-TIA at the output, and the chain also includes standard instruments such as an AWG, DCA and optical termination. The 1320nm O-band choice matches the mainstream band preference for short-reach data center interconnects (low dispersion, well suited to short distances).
11. The Scorecard: 64-Gbit/s PAM4, TDECQ 4.2dB, 0.75pJ/bit (Figure 10)
This figure shows the optical chiplet's final eye diagram results — 32-Gbit/s NRZ and 64-Gbit/s PAM4. Fig. 10(a) is the 32-Gbit/s NRZ eye and (b) the 64-Gbit/s PAM4 eye. For PAM4, a 4th-order Bessel-Thomson filter (16GHz cutoff) and 12-tap equalizer are applied. The PAM4 eye is clean, with TDECQ of 4.2dB measured at a target symbol error rate of 4.8×10⁻⁴ and estimated energy of 0.75 pJ/bit. These numbers are where the paper's "low power, high speed" claim pays off. TDECQ 4.2dB is a metric in the language of Ethernet PAM4 specs, meaning this isn't a pretty eye under custom conditions but something moving toward real standards.
12. The Receive Side, Too: A Receiver Chiplet with an Embedded TIA (Figure 11)
This figure shows the other half of the solution — the receiver chiplet, including the TIA block diagram and the 64-Gbit/s PAM4 eye after pairing it with a membrane photodetector. Fig. 11(a) is the TIA block diagram, comprising a TIA front end, a four-stage amplifier, and a single-ended-to-differential (S2D) converter with a 50-Ω output buffer. Fig. 11(b) is the 64-Gbit/s PAM4 eye measured after assembling the membrane photodetector with the substrate-embedded TIA. The receiver follows the same substrate-embedding approach, placing the TIA close to the photodetector — showing that NTT isn't just doing the transmitter, but has carried the same membrane-plus-embedded-substrate methodology through both ends of the link.
13. Technical Highlight: Splitting Power and Bandwidth into Two Variables and Beating Each
The most elegant thing about this paper is that it doesn't attack "low power, high bandwidth" as one vague goal; it splits it into two independently controllable physical variables and works each one. First, the membrane structure lowers junction capacitance. A lateral p-i-n junction plus removing the silicon waveguide in the modulator section to raise confinement drops junction capacitance from about 100fF in conventional high-mesa devices to 26fF — the source of the bare device's 67GHz and 150-Gbit/s NRZ. Second, substrate embedding shortens the electrical interconnect to a minimum, and split supply rails save power. Material structure solves bandwidth, packaging and circuits solve power — two clean, separate lines that end at 0.75 pJ/bit.
14. Industry Implications: How Far from Volume Production, and Who Benefits
Realistically, this is still a "research result" rather than a "production product": it runs under the NEDO/Post-5G program (JPNP20017) and is at prototype stage. But several signals put it closer to deployment than most papers — a four-channel array, spot-size-converter fiber coupling, dual PICs on board, and physical eye diagrams on both transmit and receive. These are evidence of "moving toward a module" rather than "showing off a single point." Who benefits? Integrated device makers on the III-V-on-Si heterogeneous integration path, and telecom/cloud players building in-house. The EAM path competes head-on with microring modulators (MRM) and thin-film lithium niobate (TFLN) in the short-reach market; NTT is betting here on the combination of "membrane III-V EAM + substrate-embedded driver."
Conclusion
The real contribution of this paper isn't another 67GHz modulator. It demonstrates a complete methodology that separates the two big pain points of short-reach optical interconnect — bandwidth and power — and beats them with material structure and packaging/circuits respectively. It then fills in every piece of the link, from the transmit-side EA-DFB, four-channel PIC and substrate-embedded driver to the receive-side embedded TIA. The 26fF vs. 100fF comparison will be a reference point cited again and again when evaluating any III-V-on-Si approach. As single lanes approach 200G and every pJ counts, the membrane approach deserves a serious place on the shortlist for 800G/1.6T optical chiplets.
References
Paper title: Membrane III-V Photonic Devices on Silicon Photonics Platform for Short-Distance Optical Interconnections. Authors: Shinji Matsuo, Tatsurou Hiraki, Tadashi Minotani, Takuma Aihara, Takuro Fujii, Yoshiho Maeda, Suguru Yamaoka, Yoshiya Shikama, Norio Sato, Tomonari Sato (NTT, Inc., Atsugi, Japan). Conference: 2026 IEEE Symposium on VLSI Technology and Circuits, 2026. DOI: 10.1109/VLSITECHNOLOGYANDCIR65830.2026.11577289.
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