With 512K-GPU clusters becoming the norm for AI factories, copper is hitting its limits. An OFC 2026 panel showed how CPO delivers a 3.5X efficiency gain, and how the 12.8T XPO rewrites the switch-density game.

As copper interconnects hit their physical limits, NPO is emerging as the practical lifeline for AI compute clusters. Tencent and Alibaba plan to start 3.2T NPO deployment by late 2026, while Huawei proposes a 7.2T spec aligned with GPU roadmaps.

When does copper run out? At OFC 2026, Meta answered with 90 million device-hours of field data: CPO cuts link power by 65% and, excluding one fixable component issue, is more than 10x more reliable than pluggable modules.

This week the market read SemiAnalysis's CPO-delay report as a death knell for optical components. It read it backwards. If CPO ramps a year later, pluggable optical modules — and the upstream EML lasers already sold out through 2027 — get an extra year of earnings. Demand hasn't weakened; only the oversold share prices have.

ZR is the meat, Coherent Lite is the bone. 2026 is the year ZR generates cash; 2028 is when Coherent Lite truly ramps. Three signals could reverse everything: whether Amazon commits, how fast LPO/CPO win sockets, and production-grade demos at OFC 2027. Taiwan's real opportunity lies in upstream components, not the DSP.

AI compute is growing 2.5X a year and electrical switching is hitting its limits. An OFC 2026 workshop showed how optical circuit switching (OCS), with its low latency and low power, is becoming a core technology for NVIDIA and the hyperscalers building next-generation AI supercomputers.

At VLSI 2026, Intel showed a fully working silicon photonics microring DWDM transceiver: 16 wavelengths at 50Gb/s each for 800Gb/s per fiber, all with BER<1e-9, at about 5.7pJ/b, with 22nm CMOS stacked directly on the photonic chip in an open-cavity package. We break down this device-to-system CPO reference design figure by figure.

Conventional EDA is hitting a bottleneck when simulating silicon photonics. At OFC 2026, GF and Cadence presented photonic-native modeling built on waveguide scattering physics, delivering 2x faster simulation and paving the way for large-scale electro-photonic integration in the 1.6T era.

AuthenX (7928) uses metalenses to widen FAU alignment tolerance to ±18µm, tackling CPO's hard-to-align, hard-to-repair, hard-to-scale problems. The technology is compelling, but who owns the "patented metalens" and whether it clears certification and yield are open questions to settle before investing.

Once the laser is moved off the chip, someone has to catch that +20 dBm high-power light. AIST shows that polymer waveguides on low-cost glass-epoxy substrates can do it: zero degradation over six hours and only a 4.4°C temperature rise — a key feasibility endorsement for the packaging-centric CPO route.

As AI training outgrows a single site, Scale Across is the new normal. How Meta defines the next generation of interconnect, why Google says "fiber is the new wavelength," and the strategy behind Lumen's push to add 41 million fiber miles.

For a decade, photonics packaging was the last mile of assembly that nobody talked about. AI has pushed it center stage, with the market set to grow from $4.5B to $14.4B in six years — driven not by transceivers but by three new tracks opening at once: CPO, AR microLED and FMCW LiDAR. Part 1 of the series lays out the big picture.

Google's eighth-generation TPU splits into two architectures for the first time. STT breaks down how TPU 8t removes the training I/O bottleneck, and how TPU 8i uses large on-chip SRAM and OCS optical circuit switching to cut MoE inference network hops by 56%.

Light leaks a little at every interface, and coupling is where CPO's optical losses concentrate, an invisible ceiling on yield and serviceability. Doubling V-groove density, edge vs. grating coupling, passive vs. active alignment: this unglamorous layer is where volume-production gaps open up.

NVIDIA proposes a symmetrical, wavelength-agnostic bidirectional silicon photonics link that uses polarization multiplexing to break CPO's port-count and cost bottlenecks. Error-free 32 Gbps bidirectional operation makes "colorless" optics a reality and paves the way for scaling AI cluster networks.

Silicon photonics interconnects are hitting an inflection point. At OFC 2026, GlobalFoundries showed how detachable connectors and 3D packaging tackle the 100+ fiber assembly challenge in AI inference, while building a complete US-based optical packaging ecosystem.

As copper can no longer keep up with the data movement demands of AI clusters, Marvell answers with its Photonic Fabric optical platform. This is not just a speed upgrade, but an architectural shift that breaks through the memory wall and the power bottleneck.

In the era of gigawatt AI factories, the network defines the computer. NVIDIA unveiled 3D-stacked silicon photonics CPO and industry-leading MRM technology to break through the power and reliability limits of AI scaling, and laid out a decade-long roadmap fusing compute and optics.

Silicon photonics' original sin is that it can't emit light. Lasers hate heat, yet CPO asks them to sit next to a hot chip — making the light source the reliability ceiling, where one failed laser can cost an entire optical engine. External vs integrated sources and four light-source types each bet on a different future.

The CPO era has officially begun, with Cignal AI forecasting a $1.5B opportunity by 2030. Beyond the push from Nvidia and Broadcom, STT argues that CoS packaging for high-power lasers is the hidden barrier that will decide who wins ELSFP volume production.