The Switch Breaks Before the GPU: Three Counterintuitive Takeaways from OCP's Open Silicon Photonics White Paper

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1. Why This White Paper Is Worth Your Time

The industry has been talking about "optics into the rack" for two years, but most of the conversation stops at single-vendor product launches or the CPO-versus-pluggable debate. This white paper does something different: it starts from physics and works through one bottleneck at a time, calculating which limit each rack configuration hits first.

The author list is a signal in itself. Lead author Bijan Nowroozi is from Lightmatter, with co-authors from Dell, Qualcomm and Flex, and contributors including GUC, Intel, Corning, Keysight, Celestica, Foxconn FIT and Jabil. This is a document signed jointly by system vendors, ODMs, an ASIC services house and a photonics startup, and it targets OCP's open ecosystem rather than any one company's closed chassis.

The paper opens with a line that frames the entire document:

Copper makes topology follow distance; optics lets topology follow the workload.

The point: with copper, which chips can talk at high speed depends on how physically close they are. With optics, distance stops being the constraint, and GPU interconnect can be designed around what the model needs.

2. Copper's Problem Isn't Speed, It's Reach and Shoreline

The white paper breaks copper's limits into three, and all three get worse with every generation.

Shrinking reach: As SerDes moves from 224G to 448G per lane, usable copper reach shrinks by roughly 2–4x under the same modulation. At 200G there is about 1 meter on the board; at 400G, under 0.5 meters; at 800G, practically any board-level distance may need a retimer.
Accumulating latency: Retimers can buy back reach, but every stage adds latency. A multi-retimer copper path accumulates about 40–120 ns, a structural latency no topology can route around.
The shoreline ceiling: How much I/O a package can escape is set by its edge length (shoreline), not its area. No amount of reach extension raises that ceiling.

The bill ultimately shows up in compute utilization. The paper cites an MFU of only 38–43% for Meta's Llama 3 405B pre-training, with most of the loss coming from communication and synchronization. Put simply: more than half the compute in an extremely expensive machine is waiting for data.

3. Counterintuitive Takeaway #1: The Switch Breaks Before the GPU

When the market talks about AI rack bottlenecks, the focus is usually the GPU: too much power, not enough HBM, CoWoS capacity constraints. But when the white paper lines up each chip's required scale-up bandwidth against the bandwidth copper can escape from the package shoreline, the result is clear:

Chip	Required scale-up bandwidth (Tb/s per direction)	Copper shoreline capacity	Result
R200 / MI400	14.4	52	Fits
R300 / MI500	40	54	Fits
TPU v7	4.8	42	Fits
102.4T switch	102.4	26	4x short
204.8T switch	204.8	26	8x short

▲ Required scale-up bandwidth per chip versus the bandwidth copper can escape from the package shoreline. Every GPU is still within copper's reach; 102.4T and 204.8T switches fall short by 4x and 8x respectively. (Source: Simple Tech Trend; data from OCP, Architecture Vision: Open Silicon Photonics for AI Systems, v1.0.6 (July 2026), Table O)

The reason is not hard to see. A GPU's scale-up demand is roughly a dozen to a few dozen Tb/s, while a switch serves an entire domain and needs 100–200 Tb/s or more. Copper escape scales with the chip's edge length, but switch demand scales with domain size, so the switch is bound to hit the ceiling first.

The white paper's verdict: the 204.8T / 1.6T generation is where copper can no longer carry switch escape bandwidth. With Area Photonic Output (APO), a switch can escape 46x the bandwidth of copper, because area scales with the square of edge length.

This matters for anyone reading CPO timelines: optics enters scale-up at the switch first, and the GPU follows a step later. It also echoes the beachfront density problem we covered in Huawei's 1024-lane switch stuck at 0.07 T/mm: the edge real estate on a switch die is the first resource to run out.

4. Counterintuitive Takeaway #2: Kyber Is Where Copper Gives Way to Optics

The white paper picks four public rack configurations as reference points, spanning 2024 to 2028:

Rack	GPUs	Rack power	Network share of power	Copper status
GB200 NVL72	72	~120–140 kW	~4–9%	Sufficient
AMD MI450 / Helios	72	~120 kW+	~11–16%	Tight
Kyber, 2 canisters	144	~400–500 kW	~31%	Flat bisection requires pluggable optics
Kyber, 4 canisters	288	800 kW–1 MW	~31%	Copper midplane not feasible

▲ GPU count and network share of power across the four rack reference points. NVL72 is still in single digits; Kyber-class jumps to about 31%, the tipping point from copper to optics. (Source: Simple Tech Trend; data from OCP, Architecture Vision: Open Silicon Photonics for AI Systems, v1.0.6 (July 2026), Table V)

The takeaway from this table is not any single number but the binding constraint is moving. At the NVL72 level copper is still sufficient, and the case for optics rests on fiber plant that can be reused across generations and on eliminating retimer latency: nice to have. At the Kyber level, the copper midplane simply fails and optics becomes mandatory. Further out, at multi-rack scale, the constraint shifts again to optical radix itself: how many fibers each switch package can escape becomes the new bottleneck.

The white paper aims to cut Kyber-class network power from about 31% to about 15%, which at that density saves roughly 100 kW per rack.

Two caveats. First, the 288-GPU, 4-canister configuration is the white paper's own 2x extrapolation to an architectural limit, not a product NVIDIA has announced. Second, there is already noise about Kyber's schedule slipping, which would push back the point where copper runs out, but would not change the direction.

5. Counterintuitive Takeaway #3: No Winners Picked, Only Contracts Defined

At this point many readers expect the white paper to tell them whether to bet on CPO, NPO or pluggables, or on SiPh, VCSEL or micro-LED. It deliberately declines to answer.

Its method is called "envelope and contract": it specifies only the interfaces and behaviors each component must meet, not how to build it. Optical engines are split along two independent axes:

Technology class: silicon photonics with external laser (SiPh-ELS), VCSEL, micro-LED, coherent, and silicon photonics with heterogeneously integrated lasers (SiPh-IL).
Placement class: CPO, NPO, socketed NPO, mezzanine NPO, and front-panel pluggable (FPO, which includes XPO).

Any technology class can pair with any placement class, as long as the link budget closes. But every combination connects to the same passive fiber plant: fiber, raceways, ODFs and optical faceplates. This plant is designed to carry across generations, unchanged through both 224G and 448G, while only the active optical engines refresh on their own cadence.

The logic is pragmatic: optical engine technology is still evolving fast, and betting on a single path now is too risky, but fiber and mechanicals stay in the data hall for many years once installed. Standardize the layer that won't change, and leave the layer that will to market competition. For the supply chain, this means the "unsexy" pieces such as fiber management, connectors and FAUs may get locked in by standards earlier than the optical engines. We saw the same signal in Corning packing 1,152 fibers into 1U: the bottleneck is moving from the chip to the assembly line.

The white paper is not entirely neutral, though. It devotes the most attention to external lasers, with dedicated sections on ELS cages, laser distribution and failure recovery, and liquid-cooled ELS, and it explicitly expects ring modulators to gradually replace MZMs as wavelength counts rise. For where external laser source specs are heading, see ECOC draws the spec line for ELS.

6. Timeline Breakdown: A Three-Phase Evolution

The white paper lays out a three-phase roadmap, with each phase building on the fiber plant installed in the previous one:

Near term: scale-out goes optical first. Existing horizontal trays replace pluggable optical modules with CPO or NPO, while scale-up stays on copper. The most important work in this phase is getting optical faceplates, ODFs and fiber plant installed.
Mid term: scale-up goes optical. Optical interconnect lets horizontal trays grow from 4 to 8 packages per tray; vertical canisters drop the copper midplane, and the scale-up domain expands to a full rack or even multiple racks. The white paper estimates that 3 racks could form an optical scale-up domain of about 1,728 XPUs.
Long term: volumetric compute arrays. XPU modules are arranged in a three-dimensional array and interconnected by optical flyovers. The white paper itself says this is a direction, not a near-term design target.

▲ The white paper's three-phase platform evolution. Phase one takes scale-out optical and pre-installs fiber plant; phase two takes scale-up optical and extends the domain across racks; phase three moves toward volumetric compute arrays. (Source: Simple Tech Trend; data from OCP, Architecture Vision: Open Silicon Photonics for AI Systems, v1.0.6 (July 2026), §9.4)

Why make the scale-up domain bigger? The white paper cites a 2025 Hot Interconnects simulation: training a 4.7T-parameter MoE model on 32,768 GPUs, replacing four 128-GPU electrically connected pods with one 512-GPU optically connected pod cut training time by 1.55–2.71x, with larger gains as the number of experts grows. MoE is precisely the dominant architecture for frontier models. On that basis the white paper sets an MFU target of 55–65%, 30–70% higher than today.

7. Where to Stay Level-Headed

This is a vision, not a spec. The white paper states that it is informative, and every "should" and "must" is directional. The actual Base Spec only gets written once an OCP workstream is formed, and going from vision to a production-ready spec is usually measured in years.
The target numbers are not yet validated. MFU of 55–65%, a 15% network share of power, and CPO-class MTBF above 2.6 million hours are all targets or simulation results. Appendix D of the white paper labels the evidence status of each key figure; some are measured, some are extrapolated.
NVIDIA is not on the author list. Kyber is the white paper's main reference point, but NVIDIA has its own NVLink and rack roadmap. Whether the open camp's standard becomes mainstream depends on actual adoption by AMD, hyperscaler in-house ASICs and the UALink camp.

Conclusion

The white paper's greatest value is turning "when will optics enter the rack" from a matter of faith into a table you can calculate. Its answer: optics enters scale-up at the switch first, in the 204.8T / 1.6T generation; the GPU side waits until Kyber-class density, once the copper midplane fails.

For anyone tracking the supply chain, two signals are worth watching:

The CPO adoption timeline for 204.8T switches. This is where the white paper calculates copper fails first.
Whether OCP formally launches a workstream. Spawning one is the white paper's whole purpose; once the Base Spec starts being written, specs for fiber plant, faceplates and external laser sources will be locked in.

In the next piece we go a layer deeper: how much fiber and how many lasers a 204.8T switch needs, how big the external laser source and passive fiber plant markets are, and which links Taiwanese suppliers are positioned in.

References

Open Compute Project, Architecture Vision: Open Silicon Photonics for AI Systems, v1.0.6, July 2026. Authors: Bijan Nowroozi (Lightmatter), Mohammad Alavirad and Jian Chen (Dell Technologies), Michael Klempa and Jared Wright (Qualcomm), Jiayin Ma (Flex). Licensed under CC BY-SA 4.0.