OCP Global Summit 2026 | Ligent Tech | Weiping Huang, Jianwei Mu | Beyond Pluggable Optics: The Emerging Role of NPO

1. Why Ligent Says NPO Is Not a Transition

The talk at this IPEC NPO workshop was credited to Ligent founder Weiping Huang, who could not attend; co-author Jianwei Mu presented on his behalf. The opening line set the position for the whole session: NPO is not a bridge from pluggables to CPO. It has already evolved into two distinct paths, one for switch network I/O and one for scale-up compute I/O.

That view lines up with what we laid out in NPO Is Not CPO's Appetizer. The difference is that Ligent does not stop at the argument: it backs the "two paths" claim with measured numbers from two of its own 3.2T optical engines.

The question is no longer whether optics moves closer to the chip, but which I/O segment should become optical and how serviceable that boundary must remain.

2. Breaking Down the Electrical Bottleneck: Channel Loss from 25 dB to 13 dB

Ligent starts from the electrical side. 224G electrical I/O is ramping now, and 448G makes the reach, power and packaging problem harder still. Citing OIF CEI-224G and OFC 2026 CEI-448G demonstrations, it lays out three architectures:

• Pluggable: 10 to 20 inches of trace from host to optical engine, about 25 dB of channel loss absorbed by an in-module DSP, roughly 15 to 20 pJ/bit.

• NPO: trace shrinks to 1 to 3 inches, loss of about 13 dB, the DSP can be removed, roughly 6 to 12 pJ/bit, with 2 to 4 times the bandwidth density.

• CPO: 0.5 to 1 inch of trace, about 8 dB of loss, roughly 5 to 10 pJ/bit, with 4 to 8 times the bandwidth density.

▲ Ligent places pluggable, NPO and CPO at three balance points: NPO trades about 13 dB of channel loss for a replaceable optical engine and openness (Image source: Ligent Tech | 2026 OCP Global Summit presentation (02:42))

The most useful line is the footnote on the same slide. Counting the laser source, management circuitry and allocated cooling power, a retimed pluggable draws about 24 W per 1.6T, NPO about 11 W and CPO about 7 W. That puts NPO about 54% below pluggables and CPO about 71% below (STT calculation): NPO captures roughly three-quarters of CPO's power saving while the optical engine can still be tested and replaced on its own.

▲ The closer the electro-optical conversion point sits to the host chip, the lower the channel loss and power per 1.6T; NPO captures about three quarters of CPO's power savings (Image source: Simple Tech Trend; data from Ligent Tech's 2026 OCP Global Summit presentation)

What these numbers say: NPO is not a "worse CPO". It trades a gap of about 4 W per 1.6T for serviceability and a decoupled supply chain. For system vendors still worried about CPO yield and after-sales models, that is a trade that pencils out.

3. Two Paths: Network NPO Optimizes the Port, Compute NPO Optimizes the XPU Boundary

Ligent lays out the differences between the two paths in one table:

Dimension	Switch-side NPO (network I/O)	XPU-side NPO (compute I/O)
What it replaces	Front-panel pluggable E/O conversion	Reach-limited copper and electrical I/O
Primary fabric	Scale-out / network fabric	Scale-up / rack or supernode fabric
Reach target	Hundreds of meters to km	Meters to tens of meters
Interoperability	Multi-vendor PMD interoperability is critical	System-level interoperability
Latency	Important	First-order constraint
Service model	Socketed, replaceable optical engine preferred	Small tiles; board or tray service acceptable
Typical product	3.2T / 6.4T / 12.8T high-capacity engines	Distributed optical I/O tiles around the XPU

On electrical architecture, Ligent's view is that retiming is not a binary choice. Linear NPO has the lowest power and latency but depends most on host SerDes and end-to-end co-design. Half-retimed designs (LRO / TRO) recover margin only where needed and suit 200G / 400G lane scaling. Fully retimed designs offer the strongest isolation and interoperability at the cost of power, latency and silicon. The conclusion: switch NPO can justify selective or full retiming, while XPU NPO leans toward linear or minimal retiming.

Product evolution also runs on two tracks. Network I/O moves from 800G / 1.6T front-panel modules to 3.2T / 6.4T socketed engines, then to 6.4T / 12.8T high-density engines with fiber shuffles and ELS / ILS, and only then to package-level integration at 12.8T and beyond. Compute I/O starts from copper, moves to NPO tiles distributed around the XPU, then to dense package-edge optical I/O, and finally to CPO / OIO chiplets.

▲ Ligent's NPO product evolution: network I/O moves from pluggables to socketed optical engines, and compute I/O moves from copper to optical I/O tiles around the XPU (Image source: Ligent Tech | 2026 OCP Global Summit presentation (09:02))

4. Breaking Down Three Implementation Choices: Laser, Interface, Packaging

Laser. An integrated laser source (ILS) avoids the external laser's PM fiber and connector path, but the laser is thermally coupled to the optical engine and a failure may require servicing the whole engine. An external laser source (ELS) can be serviced and temperature-controlled independently and decouples laser manufacturing from the engine, at the cost of coupling loss, reflection control and board or front-panel space. Ligent notes that compute I/O may have no front panel at all, which constrains ELS further. For the power and thermal side of integrated lasers, see our breakdown in CPO Lasers Don't Have to Chase 400 mW: NPO Integrated Lasers.

Interface. Ligent treats the connector not as a commodity part but as "an electrical component and a critical interface". The two options cite the ODCC UPO specification Rev 0.95 and the OpenCPX specification Rev 0.8:

• LGA / solderless socket: lowest profile, shortest electrical path, high density at the ASIC perimeter, but compression and long-term reliability are the challenges.

• OpenCPX / mezzanine: a standardized socketed direction, a simpler insertion model and a multi-vendor ecosystem, at the cost of an extra connector path in the signal-integrity budget. For the OpenCPX ecosystem, see ECOC 2026 | Ciena's Open CPX Turns the 6.4T Optical Engine Back into a Shelf Part.

Packaging. Ligent's mapping: 1.6T mostly uses 2D (PCB plus discrete PIC / EIC), 3.2T may move to 2.5D flip-chip, 6.4T to RDL with TMV or TGV, and beyond that (the transcript sounds like 12.8T) 3D hybrid bonding may be required. The slide's conclusion: as optical engines scale from 3.2T to 12.8T, competitive advantage shifts from standalone optical design to co-optimization of photonics, EIC, substrate / RDL, thermal paths, fiber attach, assembly and test.

5. Two 3.2T Engines: 23 W vs 4.5 W

This is the hardest data in the talk.

SiPh 3.2T platform (network NPO): 32 channels at 100G each, TDECQ 1.3 dB, OMA 1.3 dBm, extinction ratio 3.5 dB, measured BER across 32 channels of 1e-9 to 1e-12, and 23 W typical power. The speaker added orally that it supports about 500 m and has been shown at CIOE and ECOC (the transcript is ASR; the show names are STT's reading), and that it is the platform toward 6.4T.

▲ Ligent SiPh 3.2T NPO platform: 32 lanes, TDECQ 1.3 dB, BER 10⁻⁹ to 10⁻¹², typical power 23 W (Image source: Ligent Tech | 2026 OCP Global Summit presentation (13:10))

VCSEL 3.2T platform (compute NPO): also 32 channels, TDECQ 2.8 dB, extinction ratio 1.8 dB, measured BER of 1e-7 to 1e-8, and 4.5 W typical power.

▲ At the same 3.2T and 32 lanes, Ligent's VCSEL optical engine draws about one fifth the power of SiPh, at the cost of optical margin and BER (Image source: Simple Tech Trend; data from Ligent Tech's 2026 OCP Global Summit presentation)

In pJ/bit terms, that is about 7.2 for SiPh and about 1.4 for VCSEL (STT calculation, engine power only). The comparison makes Ligent's "two paths" argument concrete: network NPO spends power to buy margin and reach, compute NPO spends margin to buy power. The VCSEL engine's BER is two to four orders of magnitude higher and its TDECQ 1.5 dB worse; FEC can absorb that in short, controlled in-rack links, but not in network ports that need multi-vendor interoperability. For the thermal and reliability challenges on the VCSEL path, compare ECOC 2026 | VCSELs Already Hit ≤1 pJ/bit; Fiber Is What Holds Them Back.

6. Risks and Counterarguments

• Inconsistent power basis: the 24 / 11 / 7 W per 1.6T include laser, management and cooling; the 23 W and 4.5 W for the 3.2T engines are "engine power", and the slides do not say whether they include the laser or host SerDes, so the two sets cannot be compared directly.

• BER is a measured range, not a post-FEC number: the VCSEL engine's 1e-7 to 1e-8 needs FEC; real system margin depends on the SerDes and FEC architecture, which the slides do not give.

• No timeline or customers: the talk gave no production date, pricing or customer names; both engines are at the demonstration and platform stage.

• VCSEL reach and lane-rate scaling: Ligent itself lists reach, lane-rate scaling and the thermal / reliability envelope as VCSEL challenges; after 32 lanes at 100G, progress on 200G VCSELs is what decides whether compute NPO can ramp.

• Interface standards not settled: both UPO and OpenCPX are pre-Rev 1.0, and the socket and mezzanine paths may coexist for a while, which means duplicated development cost for engine makers.

7. What It Means for Taiwan's Supply Chain

• Packaging co-optimization plays to Taiwan's strengths. Ligent says plainly that beyond 3.2T, the contest is in co-optimizing photonics, EIC, substrate / RDL, thermal, fiber attach, assembly and test. RDL, TMV / TGV and hybrid bonding are processes Taiwan's foundry, advanced packaging and substrate makers have already invested in; the further engine makers push toward 6.4T and 12.8T, the more they need that capability.

• Sockets and connectors are a spec battle and a component opportunity. The slides cite both China's ODCC UPO specification and the OpenCPX specification, meaning at least two interface frameworks are advancing for NPO. Taiwanese connector and socket makers that want a position will need to track version changes in both.

• The VCSEL path brings Taiwan's compound semiconductor sector back in. The 4.5 W compute NPO engine uses directly modulated VCSELs, a different supply chain from SiPh's reliance on CW lasers. Taiwan already has VCSEL epitaxy and foundry capacity, but Ligent disclosed no suppliers, so for now this is an opportunity on the roadmap rather than an order in hand.

8. Conclusion

Ligent brought no new market numbers and no production timeline, but it did something few other NPO speakers did: it quantified the trade-off between network NPO and compute NPO with two engines from the same company at the same 3.2T. 23 W vs 4.5 W and 1e-12 vs 1e-8 are not two versions of one product; they are two different markets.

The timing needs to be read separately. Network NPO already has a 3.2T platform heading to 6.4T, with the challenges in interface specs and packaging. The VCSEL compute engine has attractive power, but ramp talk has to wait for 200G lanes and reliability data. Over the next 12 months, watch three things: measured power on Ligent's 6.4T platform, whether the VCSEL version shows 200G-lane numbers, and which of UPO or OpenCPX reaches Rev 1.0 first.

NPO's value is not how close it sits to the chip, but that it lets each application decide which segment should become optical.

This article is for technology and industry trend analysis only and does not constitute investment advice.