OCP Global Summit 2026 | Lightmatter, Dell | Bijan Nowroozi, Morris Repeta | Open Silicon Photonics for AI Systems

1. Why Lightmatter and Dell Shared the Stage

The pairing is the message: an optical I/O startup plus a top-tier server OEM. The speakers framed the split themselves: Lightmatter represents the I/O side, Dell the server side.

Lightmatter's Passage follows the 3D photonic interposer route, the "light out of the die face" path shown on the slides. What it needs most is not another proof that optics work, but system vendors willing to put optical engines into mainstream trays. Dell's need is the mirror image: a tray cannot turn into a one-off custom build for the sake of optics. In the speaker's words, a photonic tray that does amazing things but has nothing in common with everything else "is really not useful."

So the whitepaper starts conservatively: ORv3 racks as the size baseline, DC-MHS as the tray specification, plus MGX, NVIDIA's MHS-derived design, blended in where the two do not conflict. The speaker even joked that he hoped he would not get shot by certain people after the talk.

The question this talk tackles is not whether optics can run, but whether optics can become an off-the-shelf standard part.

2. Breaking Down Escape Bandwidth: The Bottleneck Is the Perimeter, Not the Chip

The first slide turns the problem into math: logic grows with area (L²), but I/O can only leave through the perimeter (L). The bigger the chip, the less perimeter per unit of logic; HBM PHYs claim the package edge first, and the fabric gets only what remains.

The XPU-side chart quantifies it:

• Full perimeter for I/O (no memory on the edge): 122 Tb/s/dir

• Half the perimeter taken by HBM: 33 Tb/s/dir, below the Gen N line of 40 Tb/s/dir

• Add an IO chiplet for D2D fan-out: back to 63 Tb/s/dir, still under Gen N+1 (80)

On the switch side there are three tiers: copper 26, CPO 93.6, APO 1,191 Tb/s/dir.

▲ Same reticle-size package and 224G lanes: copper 26, CPO 93.6 and APO 1,191 Tb/s/dir; on the XPU side, with HBM taking up the perimeter, only 33 Tb/s/dir remains (Image source: Simple Tech Trend original, data from Lightmatter and Dell's 2026 OCP Global Summit presentation)

This is the same beachfront-density problem we covered in ECOC 2026: A 1,024-Lane Switch Stuck at 0.07 T/mm. The difference is that Lightmatter pushes the conclusion up to the system level: the "explosion of modes" across XPO, NPO, CPO and Open CPX is all being forced by this perimeter bottleneck.

3. Breaking Down Seven New Problems: Once Optics Move Inboard, the Tray Must Be Redefined

While the optical engine sits in a pluggable cage, the cage handles most of the trouble for the system. Once the engine moves inboard, the tray has to take over seven jobs:

• Escape geometry: routing and keep-outs move inboard

• Faceplate: the cage no longer defines the envelope

• Internal fiber: service loops, bend radius, blind-mate

• Optical distribution: laser sourcing becomes a tray resource

• Power delivery: optical engine rails and sequencing

• Thermal: the optical engine and ASIC share one solution

• Management visibility: the cage's CMIS anchor point is gone

The whitepaper's approach is "extend DC-MHS, don't replace it." Inherited: DC-MHS modularity and tray boundaries, DC-SCM management, ORv3 power and rack. Extended: the ELS (external laser source) shelf, internal fiber routing and service, optical engine thermal envelopes, and photonic escape zones. Unchanged: platform-level interoperability at the tray boundary, with engine choice left to the vendor.

▲ The white paper divides the tray into F, M, S, C and R zones, marks mechanical, power, thermal and management specs around the edges, and leaves the middle open for vendor innovation (Image source: Lightmatter, Dell | 2026 OCP Global Summit presentation (page 4))

4. Breaking Down the Five-Dimension Contract: Three Placements, One Set of Interfaces

The whitepaper does not pick winners. It sorts optical placement into three classes: FPO (front-panel pluggable, the baseline), NPO (optical engine on the host board beside the package, in socketed S-NPO and mezzanine M-NPO variants), and CPO (optical engine inside the XPU or switch package, 2D or 3D, where the FRU is the whole package). The slide also shows XPO, Open CPX, 2D CPO and 3D CPO; for background on Open CPX see ECOC 2026: Ciena's Open CPX Turns the 6.4T Optical Engine Back into a Shelf Part.

▲ Three placement classes, FPO, NPO and CPO, mapped below to XPO, Open CPX, 2D CPO and 3D CPO (Image source: Lightmatter, Dell | 2026 OCP Global Summit presentation (page 5))

Every class has to answer the same five questions:

Dimension	FPO (front-panel)	NPO (near-package)	CPO (co-packaged)
Mechanical	Cage + faceplate envelope; pluggable service	OE keep-outs; fiber egress zones; socketed / mezzanine FRU	Package envelope; blind-mate fiber; ELS shelf; FRU = package
Power	Cage power limits	OE rails on tray; sequencing	ELS + OE package power; sequencing
High-speed signaling	Host SerDes to cage (LR-class)	Short-reach trace (XSR/VSR); unretimed to half-retimed	Unretimed XSR-class; no connector in the channel
Thermal	Faceplate airflow	Shared airflow, OE + ASIC	Package-level cooling; liquid-ready
Management	CMIS at the cage	CMIS + tray sensor extension	RAS telemetry via DC-SCM path

Two reference trays on the slides make the contract concrete: the compute tray carries more than 400 Tb/s of fiber routing, with an ELSFP cage and high-density optical connectors on the faceplate; the switch tray is 204.8T class, 512 × 400G or 1,024 × 200G, with flyover copper and photonics sharing one 1RU tray.

5. Management and Reliability: After the CMIS Anchor Disappears

This is the most underrated cell in the whole contract. Pluggable modules rely on CMIS at the cage; once the optical engine moves inboard, that anchor is gone. The whitepaper proposes a hybrid: OCP RAS telemetry covering optical engines and lasers, an OIF CMIS extension path for inboard engines, and DC-SCM tying it into one management plane. The speaker admitted this is "probably pretty hard."

The reliability numbers cite Meta: first-generation CPO fleet MTBF of 8.2 million hours, about 10x pluggables; the second generation has passed 50 million operating hours (ECOC 2025 / OFC 2026). We broke down this reliability curve in OCP APAC Summit 2026: Broadcom's Third-Generation CPO Report Card. Serviceability rests on two things: the laser as a FRU (ELS), and fiber service loops written into the mechanical spec.

6. What the Contract Buys: Scale-Up From 72 to 1,152 XPUs

Most of the benefits on the slides are whitepaper estimates and third-party citations:

Item	Electrical	Optical (contract-based design)
Network power	15–25 pJ/bit	Area-class photonics < 5 pJ/bit
Interconnect power share	~37%	~15%
Per-hop latency	Retimer 40–120 ns	Photonic hop < 10 ns
Scale-up domain	72 XPUs, 1 rack, ~1 m	1,152 XPUs, 16 racks, ~1 km

The headline is a 16x larger scale-up domain, from roughly 1,000x reach and 8x port density (source cited as SemiAnalysis 2026). Two more claims: about 10x lower straggler tail on a 512-way collective, and an MFU target of 55–65%.

▲ 72 XPUs in a copper NVLink rack versus 1,152 XPUs across racks with CPO, a 16x larger scale-up domain (Image source: Lightmatter, Dell | 2026 OCP Global Summit presentation (page 10))

Racks are planned in both orientations: ORv3 MHS horizontal Class-H at 600 kW and up, with a 72–144 XPU scale-up domain; ORv3 next-generation vertical Class-V at 1 MW and up, with 1,024–1,152+ XPUs. Both rack types share the same external interfaces and the same fiber plant.

▲ The Class-H 600 kW horizontal rack and Class-V 1 MW vertical rack share external interfaces and fiber cabling (Image source: Lightmatter, Dell | 2026 OCP Global Summit presentation (page 11))

7. Risks and Counterarguments

• Most numbers are estimates, not measurements of this tray: the 16x scale-up domain cites SemiAnalysis, reliability cites Meta, and the drop in interconnect power share from 37% to 15% is a whitepaper estimate.

• APO's 1,191 Tb/s/dir is a ceiling: computed at microbump pitch as fabric-gross bandwidth, not usable bandwidth.

• The narrative is not neutral: the contract claims vendor neutrality, yet 46x areal I/O is exactly Lightmatter Passage's selling point.

• MGX's owner was not on stage: the whitepaper folds in MGX, but if NVIDIA's own CPO/NPO roadmap does not follow, the open tray may end up as a spec for the non-NVIDIA camp only.

• The timeline is longer than the title suggests: spec drafts run through 2027; on OCP's usual cadence, multi-vendor production trays are unlikely before 2028 (our estimate). Even the speaker called the hybrid management architecture hard, and it is the most likely source of delay.

8. What It Means for Taiwan's Supply Chain

• Value shifts to tray integration. The contract makes mechanics, fiber routing, power sequencing and liquid coupling the tray's responsibility. Taiwanese server ODMs have long been the main builders of ORv3, DC-MHS and MGX racks, and whoever first ships a multi-vendor tray that meets the five-dimension contract will hold design leadership for the next generation of optical trays. The slides do not list the roughly 19 participating companies, so whether Taiwanese firms are among them cannot be confirmed.

• The laser turns from an in-package component into a replaceable standard part. Both the ELS shelf and the faceplate ELSFP cage are written into the tray contract, making the laser a formal FRU and tray resource. For Taiwan's CW laser die and epitaxy makers, this is a standardization opportunity: a standard part enables multi-sourcing, but it also means specs and reliability must be qualified first.

• Demand for fiber and connectors is certain. A single compute tray carries more than 400 Tb/s of fiber routing, and with blind-mate and service-loop rules, high-count fiber arrays and blind-mate connectors are unavoidable.

• Silicon photonics foundry work sits outside the contract. "Engine choice stays with the vendor" means the contract only guarantees that a finished engine has a place to plug in; TSMC COUPE and other SiPh platforms still have to compete at the engine level.

9. Conclusion

This talk launched no new chip, but it fills the layer CPO adoption lacks most: a platform contract that system vendors can design against. Lightmatter and Dell's judgment is clear: the perimeter bottleneck has already made inboard optics inevitable, and what really slows adoption is that every tray answers the same five questions on mechanics, power, signaling, thermal and management from scratch.

But the timeline must be split apart. The whitepaper is readable now, spec drafts run to 2027, and multi-vendor production trays are estimated for 2028 or later. Three things to watch over the next 12 months: the content of the first draft from the MHS Interconnect-for-AI workstream, NVIDIA's stance on optical extensions to MGX, and whether the management architecture (RAS + DC-SCM + CMIS) converges first.

The next contest in optics is not whose optical engine is faster, but whose optical engine fits the same contract.

This article is for technology and industry trend analysis only and does not constitute investment advice.