VLSI 2026 | Technical Paper Analysis | Intel Packs 16 Wavelengths into One Fiber: Inside an 800Gb/s, 5.7pJ/b Open-Cavity MRR-DWDM Transceiver
At VLSI 2026 (paper C20.1), Intel presented an O-band silicon photonics microring (MRR) DWDM transceiver that runs 16 wavelengths at 50Gb/s NRZ each, delivering 800Gb/s per fiber simultaneously over a single fiber with BER<1e-9 on every wavelength. It is not yet another modulator IP block, but a complete, working DWDM optical interconnect system prototype: a 16-wavelength DFB laser array, microring modulation, wavelength interleaving, Ge photodetectors and semiconductor optical amplifiers (SOA) all grown on the same photonic chip. Overall energy efficiency is about 5.7pJ/b, and an "open-cavity" organic package lets the 22nm CMOS electronic chip be 3D flip-chip stacked directly onto the photonic chip, bypassing high-speed interposer parasitics.
1. Background: Intel's VLSI 2026 Paper C20.1 Delivers a "System", Not a "Device"
First, what this paper is not. It is not a standalone electrical measurement of a microring modulator (MRM), not an isolated receiver front end, and not a simulation-only proof of concept without silicon. These three exclusions matter, because over the past five years the most common form of silicon photonics paper has been exactly that kind of patchwork measurement: a single device, a lab-grade optical path and a large external laser. This paper (Cooper S. Levy et al., Intel, presented at the 2026 IEEE VLSI Technology and Circuits Symposium, paper C20.1) goes the other way: it builds a complete dense wavelength division multiplexing (DWDM) transceiver as a working prototype, and it is a full link in which two identical transceivers are connected over single-mode fiber (SMF) and actually run 16 wavelengths simultaneously. The microring route is the only silicon photonics approach that can quickly stack up bandwidth per fiber through wavelength selectivity at iso-energy.
2. The Core Problem: Turning an Optical Engine into a Working DWDM Optical Interconnect System Prototype
In one sentence, the problem this paper tackles: how to integrate "16-wavelength lasers + modulation + demultiplexing + optical amplification + high-speed CMOS circuits + low-parasitic packaging" into one complete transceiver that actually runs 800Gb/s over fiber with BER<1e-9 on every wavelength. This is not a single-point breakthrough but a hard integration battle. The difficulty has three layers: the photonic layer (16 wavelengths must each align without crosstalk), the electronic layer (50Gb/s per wavelength drive and receive must be fast and efficient enough), and the packaging layer (high-speed electro-optical interconnect parasitics must be minimized). If any one layer fails, the link BER cannot hold.
3. Figure 1: The System Blueprint for 16 Wavelengths in One Fiber
This figure shows the system-level architecture of the whole optical transceiver (OTRX), from the 16-wavelength laser array on the transmit (TX) side to demultiplexing and photodetection on the receive (RX) side. The TX side is an integrated 16-wavelength distributed feedback (DFB) laser array with 200±40 GHz wavelength spacing, each wavelength modulated by its own microring modulator (MRM); both TX and RX use even/odd wavelength interleaving to suppress inter-wavelength crosstalk. The RX side uses microring add-drop filters (ADF) to demultiplex the incoming light, with the drop ports feeding Ge photodetectors (PD). This figure defines one complete Intel vision for CPO: collapsing an entire DWDM optical path into a module that can sit next to an XPU or switch package.
4. Figure 2: An Inverter-Based Differential Driver That Drops the Old "Stacked High-Voltage" Problem
This figure shows the per-wavelength differential high-speed optical transmitter (OTX) driver circuit in the CMOS electronic IC (EIC). The driver uses an inverter-based architecture to drive the MRM diode differentially, producing about 2Vdd peak-to-peak swing. The key is that it sidesteps the high output impedance of single-ended stacked drivers: to withstand 2Vdd, traditional stacked architectures need high-voltage-tolerant transistors, which means high output impedance and limited bandwidth. The high-speed transistors in this differential driver never see 2Vdd, so the topology scales easily with process shrinks. This shows the value of heterogeneous integration (building and optimizing the EIC and PIC separately).
5. Figure 3: Baseline Wander (BLW) Correction: AC Coupling with DC Alignment
This figure shows the transmitter's electrical baseline-wander (BLW) correction circuit: on the AC-coupled (cathode-side) driver output, a low-frequency feed-forward path DC-couples the OTX to the MRM, and a feedback circuit matches the DC-coupled swing (IT×Rbias) to the high-speed AC-coupled swing (Vdd). The MRM supports 50Gb/s NRZ at 1.5V reverse bias, requiring the differential driver to provide a 1.95V cathode bias; to avoid overvoltage, the cathode path is AC-coupled, with a DC-coupled feed-forward path added to handle the low-MHz data cutoff. The conventional approach uses a large resistor Rbias of about 80kΩ, but µA-level MRM photocurrent flowing through such a large resistor causes a significant drop of about 0.8V. Intel's feedback mechanism lets the DC path track the AC-coupled swing across process corners.
6. Figure 4: A Replica Circuit That Extracts MRM Photocurrent as the Handle for Thermal Control
This figure shows a replica circuit that extracts the MRM photocurrent iPH; the thermal control unit (TCU) locks this iPH to a calibrated target value, which uniquely sets the MRM insertion loss. A microring is extremely temperature-sensitive: its resonant wavelength drifts with temperature, and once it drifts off the laser, the link fails. Each microring therefore needs its own thermal control to lock it to its corresponding laser wavelength. Here the MRM iPH serves as the TX-side detuning indicator. This exposes the most practical hurdle for microring volume production: 16 wavelengths mean 16 TCUs, each with its own locking measurement and feedback.
7. Figure 5: Per-Wavelength Receiver with a Three-Stage Front End and 1-Tap Decision Feedback Equalization
This figure shows the per-wavelength CMOS receiver, including a three-stage analog front end (AFE) and the ADF thermal control logic. Each AFE starts with a transimpedance amplifier (TIA), followed by two transconductance/transimpedance Cherry-Hooper stages and a DC offset cancellation (dcoc) circuit. The AFE output is sampled by four quarter-rate track-and-hold (T/H) switches, amplified 2x and fed to two data slicers and one error slicer to perform 1-tap speculative decision feedback equalization (DFE). The AFE achieves 24GHz bandwidth, about 65dBΩ gain and 3µArms input noise. The dcoc also doubles as the measurement handle for RX-side thermal control, so one circuit serves two purposes.
8. Figure 6: A Quarter-Rate Sampler That Uses a Neutralized Double-Tail Latch to Extend Settling Time
This figure shows the quarter-rate sampler: T/H switches with 25% duty cycle, 2x gain, and a neutralized double-tail (DT) latch with deliberately extended settling time. In a 50Gb/s quarter-rate architecture, every sampler decision is a race against time: if the latch regenerates before the amplifier settles, it makes the wrong call. The design buys time in two ways: neutralization suppresses kickback noise in the double-tail latch, and quadrature clocks drive the two latch phases. Quadrature clocking combined with the 25% T/H duty cycle extends the settling time of the 2x preamplifier before regeneration.
9. Figure 7: Open-Cavity Packaging Buries the Photonic Chip in a Substrate Recess to Bypass Interposer Parasitics
This figure shows the 3D package of the DWDM transceiver: the photonic chip (PIC) sits in an open cavity etched into the organic substrate, and the electronic chip (EIC) is flip-chipped onto both the PIC and the substrate. Joining electronic and photonic chips traditionally requires a high-speed interposer, but the interposer itself adds parasitic capacitance and inductance that eat into high-speed signal bandwidth. Intel's approach buries the PIC in an etched recess in the substrate and 3D flip-chips the EIC directly on top, bypassing high-speed interposer parasitics. The EIC is also attached to the substrate so the CMOS circuits can draw power directly; a cold plate on top controls EIC temperature; and light couples vertically out of the PIC. This "open cavity + flip-chip" package is Intel's concrete answer to "low parasitics, no interposer".
10. Figure 8: The Output Spectrum Shows All 16 Comb Lines Lit
This figure shows the output spectrum of the DWDM optical transmitter (OTX), with 16 modulated optical carriers at a nominal 200 GHz spacing. The OTX output (16 wavelengths each modulated at 50Gb/s NRZ) is coupled into single-mode fiber and split in two, with one branch sent to an optical spectrum analyzer to capture this plot. A spectrum plot is the most intuitive health check for a DWDM system: 16 evenly spaced comb lines with uniform power mean the laser array, wavelength interleaving and ring locking are all in place. It condenses the effort behind the preceding circuit figures into one easily read result.
11. Figure 9: 50Gb/s Eye Diagrams, with Even the Edge Channels Wide Open
This figure shows 50Gb/s PRBS-15 OTX eye diagrams for the edge channels on the even and odd buses. The spectrum proves there are 16 wavelengths; the eye diagrams prove the signal quality on each wavelength is good enough. The researchers used an optical bandpass filter to select a single wavelength and captured 50Gb/s PRBS-15 eyes, deliberately picking the edge channels on both the even and odd buses; edge wavelengths usually face the worst conditions, so if they open, the whole set is stable. The extinction ratio exceeds 5dB. An extinction ratio above 5dB with a clean eye opening is the prerequisite for this 50Gb/s NRZ link to hold BER<1e-9.
[Image] Which one: Figure 9 of this paper (50Gb/s PRBS-15 eye diagrams for edge channels on even and odd buses) | Caption: Figure 9: 50 Gb/s PRBS-15 OTX eye diagrams for edge channels on even and odd buses. | Source: An 800 Gbps/Fiber Silicon Photonic Microring-Based DWDM Transceiver in an Open-Cavity Package (VLSI 2026, C20.1) - Figure 9
12. Figure 10: BLW Correction On vs. Off, a 0.35dB Difference in Eye Opening
This figure compares the improvement in 8Gb/s PRBS-31 OTX output eye opening when the transmitter baseline-wander correction circuit is enabled. The researchers deliberately used an 8Gb/s PRBS-31 pattern, whose spectral content lies far below the AC-coupling cutoff frequency, maximizing the low-frequency data cutoff problem to highlight whether the correction circuit works. With BLW correction on, the optical eye opening improves by 0.35dB. Do not underestimate that 0.35dB: in a DWDM system where every bit of link margin is hard-won, each decibel is real money. This figure turns the seemingly minor circuit of Figure 3 into a number you can write into a datasheet.
[Image] Which one: Figure 10 of this paper (PRBS-31 8Gb/s eye-opening improvement with BLW correction enabled) | Caption: Figure 10: Improvement in eye opening for PRBS-31 8 Gb/s OTX output when the TX baseline-wander correction circuit is enabled. | Source: An 800 Gbps/Fiber Silicon Photonic Microring-Based DWDM Transceiver in an Open-Cavity Package (VLSI 2026, C20.1) - Figure 10
13. Figure 11: All 16 Wavelengths Running Simultaneously with BER<1e-9, the Hard Evidence That Closes the Case
This figure shows the measured BER of the 16-wavelength DWDM link: 50Gb/s/λ transmitted simultaneously on eight even-bus and eight odd-bus lanes. Rather than measuring one wavelength at a time and stitching results together, everything runs at once, which is what brings out real inter-wavelength crosstalk and power-thermal coupling. The result: all 16 wavelengths at BER<1e-9, with worst-case received optical power at the Ge-PD of -10.9dBm. On energy efficiency: the 22nm CMOS drivers are 0.92pJ/b; the RX EIC is 3.1pJ/b; global clock distribution is 0.17pJ/b; and the PIC (including laser, SOA, and wavelength interleaving/deinterleaving tuning power, with the laser amortized across 8 fibers) is 1.69pJ/b, for a total of about 5.7pJ/b. This turns "silicon photonics DWDM for high-bandwidth, energy-efficient optical I/O" from a slogan into a measured benchmark open to scrutiny.
Conclusion
Read the 11 figures together and the value of Intel's paper lies not in any single record number but in its completeness of integration. It starts from the system blueprint (Fig. 1), then explains in turn how the transmitter drives the microrings (Fig. 2, Fig. 3), how each ring is locked to its laser (Fig. 4), how the receiver recovers and resolves weak photocurrent (Fig. 5, Fig. 6), and how the open-cavity package bypasses parasitics (Fig. 7), before nailing down the results with four measurement figures: spectrum, eye diagrams, BLW comparison and all-on BER. The paper names three winning factors: high integration of the O-band PIC, high-bandwidth EIC circuit techniques, and low-parasitic interposer-free packaging. As for the 5.7pJ/b energy efficiency, there is still room for improvement on the pJ/bit battlefield OIF has drawn for AI interconnect (the RX's 3.1pJ/b is clearly the biggest share), but as a system prototype that actually runs all 16 wavelengths at once, it has firmly established that microring DWDM is a viable packaging form.
References
Paper title: An 800 Gbps/Fiber Silicon Photonic Microring-Based DWDM Transceiver in an Open-Cavity Package. Authors: Cooper S. Levy, Jahnavi Sharma, Zhe Xuan, Duanni Huang, Junyi Gao, Songtao Liu, Xinru Wu, Xiaoxi Wang, Susnata Mondal, Sashank Krishnamurthy, Dan Lake, James E. Jaussi (Intel Corporation, USA). Conference: 2026 IEEE Symposium on VLSI Technology and Circuits, paper C20.1, 2026. DOI: 10.1109/VLSITECHNOLOGYANDCIR65830.2026.11577543.
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