At VLSI 2026, Intel showed a fully working silicon photonics microring DWDM transceiver: 16 wavelengths at 50Gb/s each for 800Gb/s per fiber, all with BER<1e-9, at about 5.7pJ/b, with 22nm CMOS stacked directly on the photonic chip in an open-cavity package. We break down this device-to-system CPO reference design figure by figure.

The AI compute race has entered its second half, and bandwidth and power are now make-or-break. Intel's OCI chiplet at OFC 2026 signals that the convergence of photonics and electronics at the chip level has arrived, rebuilding data center architecture rather than merely improving specs.

Silicon photonics gets the spotlight, but Intel's 0.9 pJ/b 108G PAM4 link shows VCSELs remain an underrated low-power path for short-reach CPO. We walk through this CICC 2026 paper section by section, figure by figure, and identify the last three miles VCSEL CPO must cover to reach volume: equalization, packaging and thermals.

Intel's ECTC 2026 paper swaps the flexible fiber array in a detachable CPO connector for a rigid glass coupler. The point is not lower loss but turning fiber alignment from on-site craft into a process-locked, manufacturable, traceable step.

CPO decks spend 90% of their time on chips, but data center operators ask one question: can you swap the fiber? The fiber array unit (FAU) is now a battleground of four coupling physics, with fifteen companies staking out positions.

After three years of hype, glass substrates finally reach the table in 2026, and the whole race hinges on one process: TGV. Why are Intel, TSMC and Samsung all betting on glass in the same year, and how can a technology with near-zero yield become the foundation of next-generation AI packaging?