Glass Substrates Are No Longer Slideware: Why the TGV Race Finally Arrives in 2026
Glass substrates have been talked about for three years, but 2026 is when they finally "reach the table." Intel's Clearwater Forest ships the world's first high-volume processor on a glass core substrate, TSMC is bringing its CoPoS glass pilot line up by mid-year, and Samsung and Absolics are breaking ground on new fabs at the same time. Three of the most important players placing the same bet in the same year is no coincidence: organic substrates have genuinely hit their limits. The choke point of the entire race comes down to one term: TGV (Through Glass Via). Whoever first lifts TGV yield from "almost zero" to production-worthy levels earns the ticket into next-generation large AI packages.
1. Why Now: Organic Substrates Hit the Limit Exactly Where AI Hurts Most
For the past decade, advanced packaging has relied on organic substrates (ABF build-up substrates). They are cheap, mature and backed by a complete supply chain. The problem is that AI has pushed package sizes to several times the reticle: CoWoS already exceeds 5x reticle area, and the next generation is heading to 9.5x and beyond. Once packages get that large, three physical limits of organic substrates blow up at once: warpage, a wiring-density ceiling, and high-frequency signal loss. The coefficient of thermal expansion (CTE) of resin is far from that of silicon; scale up the area and the temperature, and the whole substrate curls up like a baked potato chip, making back-end RDL impossible.
This is where glass shows its value: its CTE can be tuned very close to silicon, its surface is inherently flat, and its dielectric loss is extremely low. In other words, glass is not a "better organic substrate"; it is the foundation that can carry large packages.
The timing shows up in the numbers: Yole estimates the advanced packaging market will grow from US$46 billion in 2024 to more than US$79.4 billion in 2030, a 9.5% CAGR, with the IC substrate segment expanding to US$31 billion by 2030. AI and HPC are the only real engines.
2. Why Glass: Material Fundamentals and the "Square the Circle" Utilization Dividend
Glass displaces organics thanks to four material-level advantages: a tunable CTE close to silicon (avoiding warpage), a low dielectric constant and low dielectric loss (clean high-frequency signaling), high surface flatness (enabling fine line widths), and high chemical and dimensional stability (wider process tolerance).
But what really makes the financial model work is something else: panel size. A 12-inch silicon wafer offers roughly 72,900 mm² of usable area, while a glass panel can reach 515×510mm (262,700 mm², 3.6x a wafer) or even 650×550mm (357,500 mm², 4.9x). TSMC's CoPoS "square the circle" strategy follows exactly this logic: with the same process step, a square panel yields several times more usable packages than a round wafer, flattening unit cost.
3. TGV Is the Choke Point: Four Drilling Processes, and LIDE Pulls Ahead
Glass is an insulator; without vias and metal fill it is just a sheet of glass. To route signals vertically through it, you need TGV: drilling high-aspect-ratio vias into the glass and filling them with conductive metal. The yield, cost and density of the entire race are almost all gated by this TGV step.
There are four mainstream drilling processes today, and the gaps between them span orders of magnitude:
Mechanical drilling: minimum via diameter >150μm, aspect ratio <5:1, severe edge chipping. Essentially out of the race.
Direct laser ablation: via diameter around 30μm, aspect ratio around 10:1, but leaves micro-cracks and a recast layer.
Photosensitive glass: via diameter around 25μm, aspect ratio around 20:1, but material choices are limited.
LIDE (Laser-Induced Deep Etching): via diameter <10μm, aspect ratio >50:1, and very high batch throughput. Its two-step "modify + etch" approach avoids mechanical and thermal stress at the source.
LIDE is widely seen as the route most likely to support large-format, high-density volume production, and it is the approach being pushed by leaders such as Intel.
Drilling is only the first gate. The second is metallization fill and RDL. Whether copper can be filled without voids or gaps, and fine-pitch wiring built on the surface, directly determines electrical connection quality. This is where materials players such as Corning, Atotech and DuPont compete.
4. Two Competing Routes: TGV Interposer vs. Glass Core
Glass substrates are not one product but two routes. Mix them up and you will misjudge who is actually ahead.
Route 1: TGV interposers replacing silicon interposers. A glass interposer carries multiple dies, targeting the silicon interposer inside CoWoS. TSMC's CoPoS takes this panel-level route: pilot-line equipment is due by mid-year, volume production is planned for 2H 2028, and the first target is NVIDIA's Feynman, with partners including Ibiden and Innolux. Samsung, meanwhile, is testing glass for HBM4 stacked packaging.
Route 2: glass core substrates replacing organic package substrates. Intel leads this route. In early 2026, Intel shipped the world's first high-volume processor built on a glass core substrate, the Xeon 6+ "Clearwater Forest," using a "10-2-10" stack: a roughly 800μm glass core in the middle with 10 layers of high-density RDL on each side. Because the glass core's CTE nearly matches silicon, the package does not warp under thermal stress even when the cores run at full power. The same month, at NEPCON Japan, Intel also showed a thick-core glass substrate combined with dual EMIB bridges, doubling the supported package scale.
Supply is lining up too: SKC's Absolics is building a fab in Georgia, USA, targeting annual capacity of 12 million glass substrate units by 2027, with Intel, AMD and NVIDIA named as customers; Samsung Electro-Mechanics' line in Sejong is expected to start production at the end of 2026. The two routes are not mutually exclusive; they are two entry points through which glass penetrates advanced packaging, from interposer to substrate.
5. The Data: On 448 Gbps CPO, TGV Really Wins
For STT readers, the most exciting application of glass substrates is not CPUs but CPO. Here is some hard data that settles the argument.
At ECTC 2026, Singapore's Institute of Microelectronics (IME / A*STAR) presented a "direct double-sided RF probing" measurement method, comparing four vertical interconnect structures (SUB-VIA, TMV, TSV and TGV) above 110 GHz for 448 Gbps/lane performance. The low loss of glass shows clearly here: TGV's dielectric loss tangent (tan δ) is just 0.0002, the lowest of the four (TSV's silicon substrate has a dielectric constant as high as 11.9 and starts leaking signal even at low frequencies).
After normalizing all four structures to an equivalent 200μm transition height with full OE I/O design, differential insertion loss at 112 GHz was 0.13 dB for TGV, the best, versus 0.37 dB for TSV, 0.60 dB for SUB-VIA and 0.87 dB for TMV. TGV's pitch also aligns directly with 125μm EIC pads without extra fan-out routing, and the PAM4 eye opens cleanly with no equalization. The conclusion is straightforward: for the electrical I/O of next-generation high-density CPO, TGV is the most credible candidate on performance. This is exactly where glass substrates truly connect with the optical communications supply chain.
6. Where It Gets Stuck: Yield, Cracks and Warpage. The Devil Is in the Process
Having covered the potential, we need a cold splash of water; otherwise this is just another canned hype piece.
Hurdle one: yield. Industry interviews put it bluntly: TGV yield on glass substrates today is "almost zero." That is why a generation like Broadcom's Tomahawk 6 (TH6) will not rush into glass substrates. However large the high-speed signal benefits, if yield cannot hold up, you lose money. The gap between the lab and volume production is deeper than it looks.
Hurdle two: cracking and delamination. Glass is hard and brittle, and stress from back-end RDL processing easily triggers cracks at the edges. Academia is already quantifying this with finite element analysis: crack energy release rates vary significantly across glass materials (fused silica, Borofloat 33, D263, Gorilla, glass-ceramic), and glass thickness, edge clearance, ABF material and copper ratio all change crack propagation risk. Interfacial delamination in the substrate-adhesive-die stack also has to be tamed through repeated calibration with cohesive zone models. In other words, glass substrates are not simply a material swap; the entire process has to be rebuilt from scratch.
Hurdle three: warpage. This is actually home turf for glass. Corning's fusion-draw glass substrates are an order of magnitude flatter than organic substrates; at a 508×508mm panel size, glass warpage is about one-third that of organic substrates. Corning's accumulated low-warpage glass know-how (layered structures, anti-warpage patents) is the glass leader's hardest-to-replace moat.
7. Supply Chain Map: Raw Glass Is the Lifeline; Overseas Players Lead, Greater China Catches Up
Finally, let's lay out the players across the whole race, which is the most practical view for judging investment and partnership targets.
Upstream raw glass: three overseas giants, Corning, Schott and AGC, hold the vast majority of share. Corning is already shipping two glass products (temporary carriers for advanced packaging and carriers for DRAM thinning), while glass cores are in the sampling stage. Raw glass has the highest technical barrier in the chain and is the hardest to localize.
Equipment: laser drilling and electroplating are the two critical steps. DR Laser claims coverage of both wafer-level and panel-level TGV laser technology; Dongwei Technology's TGV electroplating equipment has already been delivered and accepted.
Materials: consumables such as etching additives (Tiancheng Technology) and surface cleaning agents (Jianghua Microelectronics).
Processing and manufacturing: panel makers such as BOE and Wove Optoelectronics are porting their existing large-format glass processing capabilities over.
The landscape in one sentence: overseas players lead on raw glass and earlier technology reserves, while China, Hong Kong and Taiwan are rapidly filling gaps in equipment, materials and processing; raw glass remains the hardest summit to take in the near term.
Conclusion
At its core, the glass substrate story is a "foundation replacement project." Organic substrates cannot bear the weight of large AI packages, and glass steps in with three trump cards: CTE matching, low loss and square-panel utilization. But whether it truly becomes the foundation depends entirely on when TGV yield climbs from "almost zero" past the break-even point.
2026 is a signal year, not the finish line. Intel's glass core shipments, TSMC's CoPoS pilot line and the Absolics and Samsung fab builds have moved glass substrates from slides to production lines; yet Broadcom holding back on TH6 and the unresolved yield bottleneck remind us not to treat signals as done deals. What to watch over the next year is not who else announces an entry, but three numbers: TGV volume-production yield, whether CoPoS holds its 2028 mass-production schedule, and when the first AI accelerator on a glass interposer actually ships. Once those three numbers turn, glass substrates will officially move from "race track" to "main table."
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