OFC 2026 - Intel's Silicon Photonics OCI Chiplet and Bandwidth Scaling for AI Infrastructure
At OFC 2026, the bandwidth bottleneck and the Power Wall in AI infrastructure remained the central battleground for the world's tech giants. In invited talk M4B.1, Dr. Thomas Liljeberg, General Manager of Intel's Integrated Photonics Solutions group, laid out how the Optical Compute Interconnect (OCI) chiplet is becoming key to scaling AI.
The talk was more than a spec showcase: it confirmed the inevitable shift of optical communications from "external pluggables" to "in-package integration."
Core Technology: From Ethernet CPO to the OCI Chiplet
As AI models head toward trillions of parameters, conventional copper and pluggable optical modules have hit their limits on bandwidth density and power. Intel's OCI chiplet is fundamentally different from the conventional Ethernet concept: it is designed for Compute Fabric (AI Scale-up), with the aim of replacing copper links between CPUs/GPUs.
1. Striking Energy Efficiency and Bandwidth Density
According to data disclosed by Intel, the OCI chiplet delivers a generational advantage on key metrics:
Energy efficiency: end-to-end efficiency of about 5 pJ/b, versus 17 W per 800G for retimed pluggables (about 21 pJ/b), a power reduction of more than 70%.
Shoreline density: with advanced packaging (EMIB/Si interposer), density reaches 1 Tbps/mm, far beyond the 500-800 Gbps/mm achievable under conventional SerDes limits.
Reach and latency: supports reach of more than 10 meters with added latency of < 10 ns, a strong match for the strict synchronization demands of AI clusters.
2. The Moat of Heterogeneous Integration: InP on Silicon
The core competitive edge of Intel's OCI is its silicon photonics (SiPh) heterogeneous integration technology. Unlike vendors that rely on an external light source (ELS), Intel bonds indium phosphide (InP) lasers directly onto the silicon wafer:
Integration: a single PIC (photonic integrated circuit) integrates an 8-wavelength DFB laser array, semiconductor optical amplifiers (SOAs) and ring modulators.
Reliability: with more than 40 million lasers shipped cumulatively, measured FIT rate < 0.1, addressing the market's biggest concern about light-source reliability in CPO architectures.
Wavelength control: using DWDM on a 200 GHz grid, a single fiber can carry > 1 Tb/s of bandwidth.
Supply Chain View: UCIe Meets Advanced Packaging
Intel stated clearly that OCI's success depends on re-partitioning. Conventional SerDes burn a great deal of power compensating for PCB loss, whereas OCI connects to the host chip (XPU) through the UCIe (Universal Chiplet Interconnect Express) interface.
D2D interface advantage: UCIe enables "wide and slow" parallel transmission, greatly reducing SerDes design complexity and energy (saving 3-4 pJ/bit).
Packaging strategy: using Intel's own advanced packaging, the EIC (electronic integrated circuit) is stacked with the PIC and packaged together with the CPU/GPU via a silicon bridge (Si Bridge/EMIB).
Simple Tech Trend View: Intel Defends Its Silicon Photonics Lead
Judging by the progress shown at OFC 2026, Intel is leveraging its IDM 2.0 vertical integration (in-house packaging, in-house fabs, in-house III-V materials technology) to build a very high barrier to entry.
OCI is the endgame for AI clusters: pluggable modules still dominate in 2026 (e.g., 1.6T/3.2T LPO), but once per-rack power exceeds 100kW, moving optical I/O onto chiplets is the only path to push efficiency below 5 pJ/b.
Standardization challenge: betting on UCIe is a smart choice for Intel, but ecosystem compatibility between the OCI chiplet and mainstream GPUs (e.g., NVIDIA) remains critical. If NVIDIA sticks with its closed in-house NVLink ecosystem, Intel's OCI may first land in Intel's own Gaudi line or in hyperscalers' custom silicon.
Tailwind for the packaging supply chain: wider OCI adoption will lift the premium on advanced packaging processes such as TSMC CoWoS and Intel EMIB.
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