At VLSI 2026, Intel showed a fully working silicon photonics microring DWDM transceiver: 16 wavelengths at 50Gb/s each for 800Gb/s per fiber, all with BER<1e-9, at about 5.7pJ/b, with 22nm CMOS stacked directly on the photonic chip in an open-cavity package. We break down this device-to-system CPO reference design figure by figure.

In the era of gigawatt AI factories, the network defines the computer. NVIDIA unveiled 3D-stacked silicon photonics CPO and industry-leading MRM technology to break through the power and reliability limits of AI scaling, and laid out a decade-long roadmap fusing compute and optics.

Microring DWDM has long been seen as the densest but hardest-to-control route. NVIDIA's ECOC 2026 paper takes "too hard to control" apart piece by piece: nine rings find nine lasers on a chip that can't see the spectrum, then re-shuffle live through an 80°C temperature drift, with even the forwarded-clock handover running at zero bit errors.

Five NVIDIA publications are not isolated research but one vertically integrated weapon, deliberately split into four layers. STT merges them into a single technology map: how far this optical interconnect stack is from volume production, and what shape it bends the supply chain into.

At ECOC 2026, 12 speakers weren't really arguing CPO vs pluggables — they were arguing about the SerDes at the XPU edge. Arista's XPO and Broadcom/NVIDIA CPO bet on 200G→400G PAM4; OCI and DWDM bet on slow-and-wide NRZ. 2027–2028 belongs to fast-and-narrow; slow-and-wide must wait for the gearbox tax to hit zero.

Meta, Broadcom and AMD jointly define the OCI 200G line interface spec, betting scale-up optical interconnect on micro-ring DWDM, bidirectional single fiber, external lasers and NRZ. It is a buyer-supplier alliance taking on NVIDIA's vertical integration, and its external laser clause draws a clear spec for CW DFB and ELSFP suppliers.

Optical interconnects are moving from the lab to the factory. NVIDIA and Lumentum have built the first production-ready DWDM laser array, with 7.2% wall-plug efficiency and per-channel power held within ±0.8 dB. More importantly, system-level simulation quantifies what actually drives optical link cost, as copper's ceiling makes the alternative an economic necessity.

At OFC 2026, NVIDIA showed optical I/O built on a 3D stack of a 7nm EIC and a 65nm PIC. Using clock forwarding with bandpass filtering, it breaks both the power and density bottlenecks of AI cluster interconnect, marking a new era for silicon photonics packaging.

The hidden thread of this PIC Magazine issue fits in one line: optical communications is turning into a semiconductor industry. We pull out three bottlenecks the market overlooks (test, the InP supply chain, and post-silicon-photonics materials) and flag three narrow upstream niches worth tracking.

Generative AI is driving explosive compute demand, and silicon photonics is the key to breaking transmission limits. This recap breaks down TSMC's COUPE, Elaser's ELSFP packaging, multicore fiber and automated testing to map the optical supply chain's path to volume production.