PIC Magazine Issue 2, 2026 Digest: Optical Communications Is Becoming a Semiconductor Industry, and Three Underrated Bottlenecks
Updated: 14 hours ago
On the surface, this issue of PIC Magazine is about AI pushing optics into the heart of the rack. The real hidden thread fits in one sentence: optical communications is rewriting itself with the semiconductor playbook. Test has to work like IC test, processes have to be foundry-aligned, material integration has to be wafer-scale, and architecture scaling needs its own "law." What makes the issue worth an STT reader's time is not yet another round of "CPO matters," but that it does something rare: it lays out in detail three bottlenecks the market overlooks: test, the InP supply chain, and post-silicon-photonics materials.
1. Why Now: What Blocks Volume Production Is Not Optical Design, It's Test
The cover story, written by Marvell's Andrew Yick, makes a hard argument: optical components are no longer pluggable modules but parts soldered into the XPU package. That creates brutal manufacturing economics. If a bad optical lane is only caught after the full CPO-XPU module is assembled, a large amount of silicon value has already been stacked on top, and one failed lane can scrap an entire high-value assembly.
The problem is not measurement accuracy but manufacturing efficiency at scale. Traditional optical test is a lab practice: low parallelism, custom setups, single stations, measured in minutes. It can support labs and pilot lines, but not high channel counts and volume production. The industry's answer is to "shift left" test to the wafer stage, establish KGD (Known-Good-Die), and run it on IC-grade parallel, automated ATE platforms. The article lays out an Insertion 1-5 test framework, from PIC wafer screening all the way to system level, and names actual tool sets: Teradyne UltraFLEXplus + Photon 100, Advantest V93000 EXA + MPI probe station, and Technoprobe integrated electro-optical probe cards. It closes with a line that nails it: "If it cannot be tested like an IC, it will not scale like one."
This is the most underrated piece in the issue. The market has bet everything on the "optics" in CPO, but the real hidden winners may come from optical test, the picks-and-shovels lane. Once optical engines are soldered into the package, test and alignment shift from a cost item to the choke point for yield and capacity.
This view that test and alignment are the real bottleneck matches the signals we saw when we broke down Marvell's architecture. For more context, see Breaking Through AI's Memory and Power Bottlenecks: How Marvell Photonic Fabric Reshapes Scale-Up Architecture and Earnings Call Highlights: Marvell (MRVL) | FY26 Q4.
2. Supply Chain: The Real Choke Point Is InP, Not Silicon
IDTechEx's Mika Takahashi breaks down the whole supply chain clearly and busts a common myth along the way: "silicon photonics vs. InP" is a false dichotomy. In 2026, almost every silicon photonics device contains an InP laser, so the more silicon photonics takes off, the more InP demand persists. What changes is the shape of that demand, which tilts toward simple CW (continuous-wave) lasers.
A few hard facts STT readers should remember:
About 70% of indium is concentrated in China (as a by-product of zinc). It was placed under export controls in April 2025. It is currently a licensing regime, not a full embargo, but the supply chain's fragility is plain to see.
InP is still stuck on small 2/3/4-inch wafers with low yield and high cost; Coherent and SMART Photonics are gradually pushing to 6-inch.
InP supply is highly vertically integrated and captive: Coherent and Lumentum handle everything from wafer to finished product in-house, completely unlike the distributed silicon photonics model of "TSMC / Tower / GlobalFoundries foundry → OSAT." The reason is that InP epitaxy involves a great deal of know-how, which forces manufacturing to stay in-house.
The ELS (external laser source) used in CPO needs high-power, low-noise lasers of roughly 300mW+, far above the 70mW-class CW lasers typical in silicon photonics, and only a handful of companies worldwide can make them. Lumentum's heritage in submarine-cable lasers has made it a key player. NVIDIA has already put $2B each into Lumentum and Coherent, $4B in total, to lock in supply.
The most valuable signal in this supply chain is where NVIDIA's $4B is pointed. When the king of AI picks and shovels personally locks in long-term contracts for high-power InP lasers, it effectively puts a stamp of approval on the narrow "ELS / high-power low-noise laser" niche. Another structural clue is module assembly moving to Southeast Asia (especially Thailand): Eoptolink and Innolight use Thai certificates of origin to avoid US tariffs. That is a shift in the supply chain map, not short-term news.
We have done deep dives on each of these: for the logic behind NVIDIA's bet, see The End of Compute Is Light: Why NVIDIA Spent $4B to Lock In Two Optical Leaders; for why InP is the real bottleneck, see Earnings Call Highlights: Lumentum | JPM Fireside Chat: InP Is the Real Bottleneck and A Turning Point for High-Speed Optical Materials: InP Substrate Expansion, Rare-Earth Policy and PD Packaging.
3. Materials and Architecture: Three "Post-Silicon-Photonics" Routes Compete
This issue puts three next-generation routes side by side, which makes them easy to compare. The key point is that they solve problems at different layers; this is not a mutually exclusive, zero-sum race.
3-1. TFLN (Thin-Film Lithium Niobate): Ligentec × UCSD
Using wafer bonding, lithium niobate and low-loss SiN are processed separately, each at its optimal temperature, then bonded together at low temperature. The pain point is clear: stoichiometric SiN needs high-temperature LPCVD to reach losses below 0.2 dB/m, but lithium niobate starts degrading at 550°C, and lithium contaminates CMOS, so monolithic integration has never worked.
The real innovation is hybrid mode: the LN is not etched at all. The optical mode is defined by the underlying SiN waveguide and couples vertically into the LN only where needed, avoiding etch damage to the crystal and its electro-optic coefficient. The results: a 110 GHz modulator, VπL of 3.8 V·cm, and 95% wafer-bonding yield. In January 2026 it signed an industrialisation partnership with X-FAB on a 200mm process.
3-2. EO Polymer (Electro-Optic Polymer): Lightwave Logic
The pitch is a very large electro-optic coefficient (hundreds of pm/V) and drive voltage below 1V. The article draws an analogy to OLED, which went from lab to volume production on the back of encapsulation technology: EO polymer's long-term reliability problems come mainly from oxygen and moisture rather than inherent material fragility, so once the failure mechanisms are understood, packaging can solve them. The core selling point is compatibility with existing silicon photonics foundry flows plus inclusion in PDKs, with no need to rebuild production lines, and it is already showing an advantage at 200 Gbit/s lane rates.
3-3. DWDM "Slow and Wide": Scintil Photonics
This is the piece STT readers should circle. In March 2026, six companies (AMD, Broadcom, Meta, Microsoft, NVIDIA and OpenAI) formed an alliance (OCI MSA) and set the spec for scale-up optical interconnect: NRZ + wavelength division multiplexing (WDM).
The core idea is not to force up the modulation rate (the PAM-4 path costs latency, power and heat) but to stack bandwidth through wavelength count: 4 → 8 → 16 → 32. Each added wavelength leaves per-channel electronics and fiber unchanged; only the light source has to scale. The article likens this to a third scaling law in semiconductor history: Dennard scaling delivered the frequency dividend, Moore's Law delivered the transistor-cost dividend, and wavelength count, through heterogeneous integration, gives photonics its own compounding curve. Scintil, using SHIP heterogeneous integration validated at Tower, has already built a 16-wavelength single-chip DWDM laser.
Don't read these three as winner-takes-all. TFLN and EO polymer are competing as modulator materials; DWDM is competing at the architecture level, and they can coexist. But if one direction is already settled, it is slow-and-wide DWDM. When the six most influential companies sign off together, the industry debate is effectively over; what remains is how fast it climbs from 4 to 16 wavelengths. The deciding factor is the multi-wavelength light source: whoever drives down the marginal cost of adding the next wavelength gets to set the architecture.
We have separate breakdowns of all three routes: for TFLN's volume inflection, see OFC 2026: TFLN's Industry Inflection Arrives, Scaling Production and the 1.6T/3.2T Deployment Path; for EO polymer, see Earnings Call Highlights: Lightwave Logic (LWLG) | 2026 Q1; for DWDM architecture and the six-giant power play, see OFC 2026: New AI/ML Interconnect Architectures, the CPO, NPO and OCI-MSA Power Play, NVIDIA's Silicon Photonics Bombshell at ISSCC 2026: 3D Stacking and Low-Latency DWDM Links, and OFC 2026: 16-Wavelength 800-Gbps Bidirectional Silicon Photonics Interconnect, Lightmatter.
4. Other News Worth a Glance
Eindhoven breaks ground on the world's first 6-inch InP volume production line: led by TNO within the PIXEurope framework and backed by €150M from the European Chips Act; Coherent is also pushing 6-inch in Texas and Sweden. Europe wants to claim a position in photonics.
NVIDIA GTC confirms Spectrum-X goes CPO: the COUPE process is a collaboration with TSMC, and Vera Rubin Ultra, NVL576 and Kyber NVL1152 start bringing photonics into the core.
ELS becomes key to CPO scaling: Sivers, O-Net and Enablence are jointly developing ELS modules that move temperature-sensitive lasers away from the hot processing units.
Quantum drives the PIC market: IDTechEx estimates PICs for quantum will reach $12.6B by 2046, with materials moving toward SiN / TFLN / BaTiO3.
NIST uses HCB (hydroxide catalysis bonding, originally from NASA) for radiation-hardened, ultra-high-vacuum, cryogenic photonic packaging aimed at quantum, space and nuclear instrumentation.
3D-printed plugs simplify fiber coupling: Heidelberg University uses a plug-like interface that needs no active alignment, already validated on a 17-port neuromorphic photonic processor.
5. Industry Takeaway: Whoever Lowers the Marginal Cost of "the Next One" Defines the Volume Era
The whole issue boils down to one sentence: optical communications is becoming a semiconductor industry.
Test must work like IC test (shift-left, KGD, ATE), processes must be foundry-aligned (TFLN-on-SiN on 200mm, EO polymer in PDKs), material integration must be wafer-scale (wafer bonding, heterogeneous integration), and architecture scaling needs its own law (wavelength count). All four point to the same conclusion: whoever can fit photonics into existing semiconductor infrastructure and drive down the marginal cost of "the next wavelength" and "the next test" will hold the power to define optical communications in the volume era.
The takeaway for STT readers is concrete: beyond watching the "optics" in optical modules and CPO, three narrow upstream niches are what this issue really flags: test and alignment (picks and shovels), high-power ELS lasers (NVIDIA has already placed its bet), and multi-wavelength light sources (the architecture decider). For the full picture, see Must-Read for 2026 AI Infrastructure: The Complete Optical Communications and CPO Supply Chain Map.
This article is a technology and industry trend digest and does not constitute investment advice.
Comments