The 3D Photonic Integration Divide: OpenLight CEO on Five Gates That Must Converge — and Why Scale-Up Is CPO's Real Window

3D photonic integration is not simply about "packing components closer together." Only when five manufacturing gates — thermal, laser, yield, reliability and alignment — converge at the same time does the real timeline of this race come into view. And scale-up networking will be its first volume application.

When NVIDIA laid out its CPO timeline at GTC 2025, the entire optical communications industry suddenly had a coordinate it had to align to. The problem: when people talk about 3D photonic integration, they are not talking about the same thing. In an interview with IEEE, OpenLight Photonics CEO Adam Carter turned the industry's biggest gray area into black and white — what true 3D is, what is merely 2.5D dressed up as 3D, and why that distinction will decide who makes it to 2030.

1. 3D Is Not a Marketing Term — It Is the Fundamental Divide Between Vertical Stacking and Side-by-Side

The first misconception to unpack: most of what the industry calls "3D photonic integration" today is actually 2.5D.

Adam Carter's definition is clean — true 3D stacks the electronic IC and the photonic IC vertically, with the driver, PIC (Photonic Integrated Circuit) and logic layers aligned on top of one another; 2.5D places the same components on a shared substrate side by side. No matter how thin the substrate or how fine the bump pitch, it is still fundamentally a lateral layout.

In engineering terms the difference looks like one word — "stacked" versus "side by side" — but at the system level it is night and day: vertical stacking lets channel count grow in the z-direction instead of fighting over lateral wafer area, while side-by-side architectures are hard-bound by substrate area, coupling distance and fanout routing. As we broke down in Technical analysis | Marvell 2.5D heterogeneous integration: the evolution of SiPh engines and optical transceivers, 2.5D is already the engineering vocabulary mainstream OSATs and PIC makers know best, while true 3D workflows are still at the trial stage marked by NVIDIA GTC 2025 and Broadcom's early CPO announcements.

Carter doesn't dodge this: "Vertically stacked electro-optical systems are still in early development." For Taiwan's supply chain, the implication is that no one has yet shown a production-grade vertically stacked architecture for so-called 3D CPO — everything shipping in volume today is "very close 2.5D."

2. Density Is 3D's Core Advantage — but Lasers and Heat Are Its Achilles' Heel

If 3D is this hard, why must the industry do it? Carter's answer is one word: density.

The value of 3D stacking is not faster performance but how many channels fit into the same area. As lane counts explode with 800G/1.6T, planar layouts will hit their limit sooner or later, and 3D is the only answer in the z-direction. But there's a catch — the laser won't come aboard.

InP (indium phosphide) lasers are extremely temperature-sensitive. Placing an InP DFB beneath the driver and logic layers in a 3D stack means putting one heat source right next to another. Carter notes that silicon photonics Mach-Zehnder modulators and InP EAMs (electro-absorption modulators) can tolerate hotter environments, but InP laser sources "currently cannot be placed next to high-power components". That is why nearly every high-density CPO concept today uses an external laser source (ELSFP) — moving the light source outside is precisely how the heat problem gets thrown out of the stack.

We covered this laser-and-heat dilemma in more depth in Earnings highlights: Lumentum | JPM 54th Global Technology Conference fireside chat — from boom-bust to structural multi-year growth, InP is the real bottleneck: InP yield and capacity are not a short-term issue but the core bottleneck every CPO player must work around for the next three years. 3D integration can deliver the headline density number, but the price is moving the laser outside at the system-design stage — which is why ELSFP and NPO will stick around for quite a while.

3. Manufacturing Yield Has No Single Bottleneck — Five Gates Must Converge Together

Asked what the single biggest manufacturing bottleneck is, Carter gave a counterintuitive answer: there isn't one.

The manufacturability of 3D photonic integration is determined by five metrics at once — yield, alignment, thermal, testing and reliability. None is a deal-breaker on its own, but all must converge before volume ramps. Carter's ranking of these five gates is worth noting:

• Yield: the more functions you stack, the more yield drops. But silicon platforms inherit mature semiconductor processes, making this one relatively "controllable."

• Alignment: with an external laser, optical coupling loss and power splitting across multiple waveguides are the most sensitive factors — and get harder as channel count rises.

• Thermal: depends on the material platform. Silicon photonics can withstand higher temperatures; architectures that include InP lasers are clearly constrained.

• Testing: expected to shift from component level to system level. As long as specs are clearly defined, it is not a fundamental obstacle.

• Reliability: non-negotiable. Long-deployed network equipment demands extremely low failure rates and very long lifetimes; the more channels, the higher the replacement cost.

In other words, the industry likes to ask "which gate is hardest," but Carter's view is that reliability and alignment are the two most sensitive right now. Yield is backstopped by silicon processes, testing has standards to follow, and thermal depends on material choice; only reliability and alignment directly decide whether CPO can run in a hyperscaler data center for five years without incident.

4. The Integration Route Battle: Why TSV and Die Stacking Are Winning — For Now

Among wafer bonding, die stacking, monolithic 3D and photonic wire bonding, Carter gives a clear interim verdict: above 200Gbps/lane, photonic wire bonding breaks down, and TSV (through-silicon via) is currently the most promising solution.

The reasons are practical. Photonic wire bonding looks great in low-speed demos, but once lane bandwidth passes 200G, loss and reflection can't be kept in check. Wafer bonding works for single-layer heterogeneous integration, but scalability across multi-layer stacks hasn't been proven. Conventional bump bonding is the workhorse of 2.5D, but pitch scaling and warpage become pressure points in multi-die stacks. That leaves TSV — using through-silicon vias to connect multiple EICs (electronic ICs) and PICs vertically.

Carter points out that Tower Semiconductor has already demonstrated TSV on a silicon photonics process, meaning the die stacking + TSV path is not just academic papers but something foundries can already run. For Taiwanese suppliers, the implicit message of this route is: the supply-chain split between separately fabricated EIC/PIC and TSV/CoWoS-level package integration will become more pronounced — PIC foundries (such as GFS and Tower) capture wafer-level orders, while CoWoS-class packaging houses capture 3D stacking orders, and these will not be the same players.

5. EDA/PDA Tools Haven't Caught Up — What 3D Really Lacks Is a Unified Co-Design Environment

The most overlooked bottleneck in 3D photonic integration is actually tooling.

Carter is blunt: "Synopsys and Cadence currently offer component-level photonic simulation; 3D applications need a unified co-design environment spanning the optical, electrical, thermal and mechanical domains." When the driver sits under the PIC and the laser sits next to the GPU, heat transfer, mechanical stress, package deformation and optical coupling inside the stack all affect one another — yet no tool today can run simulations of all four domains in a single flow.

For the two EDA leaders this is both an opportunity and a pressure point. For 3D CPO players it is a direct schedule risk — until co-design tools arrive, every new architecture requires extensive physical validation, which is the root cause of high NRE, slow iteration and drawn-out yield learning curves. The industry has been chanting "photonics will follow Moore's Law like electronics did" for a decade, but until EDA catches up, it remains just a slogan.

6. Scale-Up Is 3D's First Volume Application

So where is the first pot of gold for 3D photonic integration? Carter's answer is unsurprising — CPO, and specifically scale-up networking.

The industry used to see CPO as something that sits next to the switch ASIC, but once NVIDIA moved to bring optics into NVLink and handed GPU-to-GPU links to optics, the whole story flipped. Carter cites an industry estimate: scale-up optical interconnect volume will be 7–10x that of scale-out — because scale-out involves a limited number of ToR-to-ToR and leaf-to-spine links, while in scale-up every GPU in the rack needs its own optical connection.

We laid out the full supply-chain logic of this volume gap in Breaking through AI's memory and power walls: how Marvell Photonic Fabric™ reshapes scale-up architecture | SiPh resource pooling explained: once scale-up goes optical, PICs, drivers, CW lasers, ELSFP, fiber coupling and CoWoS-class packaging houses all benefit, at a volume an order of magnitude above pluggables. And TSMC's COUPE is the key gate that truly unlocks this volume — as we noted in CPO's first commercial year officially begins — TSMC COUPE mass production and the 200G EML bottleneck draw the 2026 optical winners and losers, 2026 W21 marks the first time this supply chain showed a winners-versus-losers split.

Carter's view aligns with our observations: the first high-volume application of 3D photonic integration is CPO linking SerDes to GPUs/CPUs, with scale-up 7–10x larger than scale-out. Getting there requires packaging yield and system-level reliability to converge together — which brings us back to the five gates in Section 3.

7. In 3–5 Years, the Real Inflection Is Copper's Exit and the Replacement of Pluggables

The real inflection point is not CPO shipments — it is copper disappearing and pluggables being replaced.

How can the 3D photonic integration industry tell where it stands? Carter gives two signals that must happen together: (1) high-performance links stop using copper entirely; (2) rack-to-rack pluggable optics are replaced by integrated 3D solutions.

Neither will happen in 2026, but if both happen together within 3–5 years, it means 3D photonic integration has moved from "early adoption" to "broad industrial deployment." Simple Tech Trend's view: 2027 is the year of divergence, 2028 the year of ramp, and 2030 the year of elimination. Vendors that never reach true 3D integration (players stuck upgrading 2.5D pluggables) will be washed out in 2028–2030, while those that position early in TSV, ELSFP and CoWoS-class 3D stacking will capture the 7–10x volume dividend of scale-up.

Signals worth tracking:

• EDA: when Synopsys / Cadence launch a unified optical-electrical-thermal-mechanical co-design environment

• Process: the yield curve of TSV on silicon photonics wafers (Tower, TSMC and GFS are the ones to watch)

• Laser: whether InP lasers' heat tolerance allows them inside the stack, or ELSFP remains a permanent stopgap

• System: deployment pace of GPU racks with optical scale-up from 2026 Q4 to 2027 Q2

3D photonic integration is not a marketing term — it is the reshuffler of the optical supply chain over the next five years. Whoever gets all five gates to converge together will win the scale-up pot of gold.

This article is for technology and industry trend analysis only and does not constitute investment advice. Original source: Adam Carter's interview with IEEE (IEEE Xplore Document 11481188).