CPO isn't stalled because the components can't be built, but because packaging has switched to an entirely new method. Once the optical engine moves onto the ASIC substrate, photonic packaging must become semiconductor-grade. Whoever standardizes it for foundries and OSATs controls the CPO timeline.

Marvell's 2.5D heterogeneous integration uses a via-last TSV process to free silicon photonics engines from wire bonds, keeping clean signal integrity at 100 Gbaud while pushing energy efficiency toward 5 pJ/bit.

True 3D means vertical stacking; 2.5D just places dies side by side — and that distinction decides who survives to 2030. OpenLight CEO Adam Carter names five gates that must converge (yield, alignment, thermal, testing, reliability) and flags scale-up as 3D's first volume window, 7–10x larger than scale-out.