[CPO Deep Dive 2/6] The Paradigm Shift in Photonic Packaging: Why CPO Is an Advanced Packaging War
CPO keeps stalling at the door, and the real difficulty isn't that silicon photonics can't be made or that lasers won't light up. It's "how to assemble them into a package that can be mass-produced." When the optical engine moves from beside the switch onto the same substrate as the ASIC, photonic packaging is forced to upgrade from "hand-assembled modules" to "packaging done the way chips are made" — a wholesale change in methodology. Whoever can stack the PIC on the EIC, and standardize it so foundries and OSATs can replicate it at scale, controls the CPO timeline. This article breaks down the three routes, one pyramid and one volume-production gate in this packaging war.
1. CPO's Hard Birth: The Problem Is "How to Put It Together," Not "Whether Light Can Be Made"
For the past three years, the CPO debate has revolved around two protagonists: silicon photonics (SiPh) yield and laser source reliability. Both matter, but neither explains a contradiction — individual components have long been buildable and samples have been lit up one after another, so why does the volume schedule keep slipping?
The answer lies in the middle layer nobody likes to talk about: packaging.
Pluggable optical modules sustained the data center for two decades not just because of good specs, but because of a module assembly supply chain honed to perfection — aligning, attaching, encapsulating and testing laser dies, fiber arrays, SiPh chips, prisms and photodiodes one piece at a time. This flow is highly customized and full of each vendor's proprietary "touch," and it was perfectly adequate in the pluggable era.
But CPO moves the optical engine (OE) from the switch faceplate onto the same package substrate as the switch ASIC, shrinking the distance from tens of centimeters to a few millimeters. That move turns the problem of "assembling a module" into the problem of "integrating optics and electronics inside an advanced package." The same task at a different scale demands an entirely different methodology.
What really changes is not the components, but the methodology of packaging.
2. Everyone Thinks the Problem Is Yield, Lasers or Heat — the Core Is a Whole New Process
Let's first rule out a few common misreadings.
Many assume CPO's bottleneck is SiPh yield — but SiPh wafer yield at mature fabs is more stable than most people think. Others blame the laser (a genuine pain point, which we'll cover in a separate piece), but laser reliability is a "component" problem, not a "why can't it be assembled" problem. Still others point to thermal — heat is certainly hard, but it is hard precisely because the entire package structure has changed.
Pull these threads together and they point to the same core: CPO forces photonic packaging to upgrade from module-level assembly to semiconductor advanced packaging.
That sounds abstract, but in practice it is a very concrete shift. In the pluggable era, an optical module is "several finished parts aligned and attached together"; in CPO, the PIC must be stacked directly with the electrical IC (EIC), using 2.5D/3D packaging, TSV (through-silicon via), micro-bumps and even direct copper-to-copper (Cu-Cu) bonding — processes once reserved for high-end logic chips.
In other words, the optical engine is turning into an "advanced-packaged chip." And the home turf for these processes is not traditional optical module makers but foundries and OSATs (outsourced semiconductor assembly and test). That is why you see the leading foundry suddenly so aggressive about CPO — the battlefield has moved to its doorstep.
3. First, Understand the Pyramid: Photonic Packaging Is Five Stacked Levels
To discuss the battle over CPO packaging routes, we first need a map. Photonic packaging is not a single step but a five-level pyramid, which from bottom to top is roughly:
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