OFC 2026 - New AI/ML Interconnect Architectures: The CPO, NPO and OCI-MSA Power Play - Oracle, Meta, Microsoft, AMD, Arista

2 days ago

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The IEEE panel at OFC 2026 was once again the center of attention. As AI shifts from pure training to continuous inference and autonomous AI agents, compute demand is moving from Exascale toward Yottascale (10 million exaflops). The session not only defined the physical-layer architecture of next-generation AI superclusters, but also exposed the fierce tug-of-war hyperscalers face between "performance" and "serviceability."

Core Technical Views: Breaking Down the Strategies of Five Giants

The session was led by end users Oracle, Meta and Microsoft, joined by chip giant AMD and switching leader Arista, to discuss the evolution path of optical interconnects.

1. Oracle: Reliability Is the Only Metric for Revenue

Oracle OCI architect Mark Filer noted that OCI's AI clusters have grown from 16,000 GPUs in 2020 to 131,000 GPUs in 2026.

Core pain point: RDMA traffic is extremely sensitive to link flaps; at large cluster scale, low-probability events become a frequent norm.
CPO as the savior: Oracle sees manual handling of pluggable modules as a major failure mode. Through high integration, CPO is expected to improve system FIT (failures in time) performance and save as much as 50% of power in the 200G/lane generation.
Technical caution: Mark voiced concern about "soldered-down" CPO, arguing it creates supply-chain lock-in and an excessively large blast radius for repairs.

2. Meta: Optical Backplanes and an Expanding Scale-up Domain

Meta network architect Rob Stone stressed that to support complex models such as Mixture of Experts (MoE), the scale-up domain (accelerator-to-accelerator interconnect) must expand from a single rack to multiple racks.

OCI-MSA: Meta, AMD and others are jointly driving the OCI-MSA specification, which uses a low-speed parallel 50G NRZ scheme to achieve low-power, low-latency optical interconnect between nodes.
Optical backplane (OBP): Meta proposed a rack concept based on "blind-mate, non-contact, contamination-resistant connectors." This can cut replacement time after a system failure from hours to minutes.

3. Microsoft: Data-Driven Technology Selection Criteria

Microsoft's Benjamin Foo presented a highly useful technology comparison table, quantifying the options for the 100G SerDes generation:

Technology path	Hardware reliability	Estimated power (pJ/bit)	Observability (telemetry)
LRO (linear receive optics)	Known failure rates, easy to service	10–14	Full optical/electrical-side telemetry
LPO (linear pluggable optics)	Known failure rates, easy to service	6–8	Limited telemetry
NPO (near-packaged optics)	Large blast radius, limits field repair	3–4	Relies on optical telemetry
CPO (co-packaged optics)	Large blast radius, limits field repair	2–3	Lacks host-side monitoring

Microsoft's position is clear: although CPO has the lowest power, if it comes at the cost of reliability and telemetry, Microsoft would rather choose a slightly higher-power solution with a mature ecosystem.

4. AMD: A Full Pivot from GPUs to Optical Interconnect

AMD's Shahab Ardalan noted that AI inference token demand has grown 100x over the past two years.

Compute density: AMD's newly launched MI350 delivers nearly twice the compute of MI300 in the same package size, forcing interconnect bandwidth to leap in step.
OCI-MSA production timeline: AMD expects the first-generation OCI-MSA specification to be finalized in March 2026, pushing the industry toward standardized bidirectional single-fiber (Bi-Di) and wavelength-division multiplexing (WDM) paths.

5. Arista: Defender of Open CPO

Arista senior director Sunil Priyadarshi launched the sharpest attack on "soldered-down solutions," calling them "brutal treatment" of optical properties.

Open CPX MSA: Arista advocates socketed CPO. This lets optical engines be swapped like a CPU, avoiding the need to scrap an entire high-value switch ASIC because of a single failed lane.
Integrated laser source (ILS) advantage: Arista argues that integrated lasers reduce interface coupling loss; compared with an external laser source (ELS), they not only save power but also free up 33% of faceplate space.

Supply Chain View: Consensus and Divergence

Consensus:

The 224G tipping point: all speakers agreed that 224G/lane will be the key moment for CPO to enter commercial pilots.
Contamination-resistant connector technology: expanded-beam connectors are seen as a prerequisite for solving CPO's serviceability nightmare, cutting insertion force by 20x and being immune to dust.

Divergence:

Laser placement: external lasers (ELS) are easy to replace but less efficient; integrated lasers (ILS) are more efficient but constrained by package thermal effects.
Packaging format: Arista insists on socketed designs to ensure a multi-vendor ecosystem, while some chip suppliers prefer soldered-down designs to fully optimize signal integrity.

Simple Tech Trend View:

From this top-level OFC 2026 dialogue, we can see AI optical interconnect is in a "chaotic transition period from modules to packages."

The disruptive force of OCI-MSA: the OCI-MSA pushed hard by AMD and Meta shows hyperscalers' ambition to bypass traditional module makers and define silicon photonics chip specs directly. This will put heavy disintermediation pressure on traditional optical transceiver vendors (such as Coherent and Lumentum).
Reliability replaces power as the new god: the remarks from Microsoft and Oracle set the tone for future procurement logic — if CPO's operating costs (OpEx) from higher failure rates offset the power savings, hyperscalers will not hesitate to embrace transitional solutions such as LRO.
The rise of packaging and test (OSAT): as CPO and NPO go mainstream, the technical crux will shift from optical design to "complex packaging yield." TSMC's CoWoS and silicon photonics integration platforms will become the optical communications industry's new chokepoint.

Key things to watch over the next 12 months: concrete data in the first-generation OCI-MSA specification and tape-out news for related silicon photonics chips.