ECOC 2026 | Fast & Narrow vs Slow & Wide: The Scale-Up Optical Interconnect Race Hinges on the SerDes at the Chip Edge
ECOC 2026's opening Symposium, "Winning Interconnects for AI," ran two halves with 12 speakers — NVIDIA, Broadcom, Microsoft, Marvell, Arista, Cerebras, Nokia, Corning, imec, Tyndall, TeraHop and Scintil — and they were really arguing about one question: should scale-up follow SerDes all the way to 400G PAM4?
The Fast & Narrow camp: Arista's XPO pushes pluggables to 12.8T/25.6T with liquid cooling; Broadcom and NVIDIA use CPO to build 102.4T switches at <4 pJ/bit, with 10x better MTBF than pluggables.
The Slow & Wide camp: OCI MSA runs 200G over a single fiber with 4λ × 50G NRZ bidirectional; NVIDIA has already demonstrated 8λ DWDM; Broadcom's VCSEL NPO hits 1.5 pJ/bit.
The dividing line isn't "CPO or pluggable" — it's the electrical interface at the XPU edge. As long as the chip has to feed both copper and optics, 200G/400G PAM4 SerDes won't retire, and every slow-and-wide link must first pay an inverse-gearbox tax of roughly 4 pJ/bit. Based on the speakers' timelines, 2027–2028 belongs to fast-and-narrow; slow-and-wide won't reach volume production until 2029–2030.
The live poll leaned the same way: after the session, the share expecting CPO within three years rose from 11% to 34%, PAM4 rose from 46% to 54%, and fewer people bet on NRZ.
1. Same audience, different answers two and a half hours later
Moderator Daniel Kuchta (NVIDIA) opened with a Kahoot poll and asked the same three questions again before the close. The first round used a free account that only fit about 54 people; the second round used a paid account and participation jumped to about 170. The samples aren't fully comparable, but the direction is clear.
Three shifts worth noting:
"Stay pluggable" fell from 26% to 9%. After Arista's XPO talk, people no longer believed pluggables would stand still — because XPO itself is a major overhaul of the pluggable.
CPO rose from 11% to 34%; NPO stayed in first place but fell from 59% to 44%. Broadcom's and NVIDIA's volume-production data won some people over.
Modulation went from a 46%/46% tie between NRZ and PAM4 to PAM4 54%, NRZ 36%. This was the most interesting signal of the day: slow-and-wide NRZ is theoretically the most power-efficient, but engineers came back to reality and bet on SerDes inertia.
As for "the most important metric," pJ/bit held first place at 45%. Andy Bechtolsheim (Arista) openly disagreed on stage, saying his answer was cost. That split is the whole Symposium in miniature.
2. Why the fight is happening now: copper reach halves every generation
The problem starts not with optics but with copper. Marvell's Claudia Hössbacher gave a brutal set of numbers: going from 100G to 200G per lane, usable passive copper reach drops from 5 m to 2.5 m; at 400G it's 1.25 m, at 800G 0.6 m, and at 1.6T just 0.3 m. A single rack is already 2 m tall.
Scale is growing at the same time. Marvell's interconnect counts: 25,000 XPUs need 75,000 interconnects; 100,000 XPUs in 2024 need 500,000; at 1 million XPUs it will be more than 10 million. Interconnect count grows faster than XPU count.
imec's Peter Ossieur ran the power math and put it even more bluntly:
2026 scale-up interface: 14.4 Tb/s in each direction over a 1 m copper backplane at 4.5 pJ/bit, about 65 W.
2035 projection: about 480 Tb/s in each direction over 10 m; even with 5.0 pJ/bit CPO, the scale-up interface alone burns about 2.4 kW — while the XPU itself is already about 4.5 kW.
Reach is halved by speed, power is multiplied by bandwidth. Scale-up moving from in-rack copper to cross-rack optics is now an arithmetic problem, not a matter of faith.
NVIDIA's Ling Liao confirmed this: today's passive copper for scale-up only reaches 1–2 m, and NVIDIA has built an NVL576 prototype system (8 racks) with copper inside the rack and optics between racks. Her wording was precise: optics isn't replacing copper, it's filling in where copper can't reach. That matches our earlier conclusion in SemiAnalysis: Copper vs. Optics Is a False Dichotomy.
3. Two ways to live: whose SerDes bends to whom
Lay out all 12 speakers' proposals and there are only two paths; the difference is who accommodates whom.
Fast & Narrow: optics accommodates the chip. It rides 200G → 400G PAM4 SerDes; optics can be DR8, BiDi, LPO, LRO, or CPO. The upside is access to the entire pluggable ecosystem, and the same optics can double for scale-out.
Slow & Wide: the chip accommodates optics. Bandwidth is split into many 50G/100G NRZ lanes, with width restored by DWDM wavelengths, VCSEL arrays, µLEDs or 3D optical I/O. The upside is no DSP, low pJ/bit and latency, and room for redundant lanes.
Arista summed up the 10–20 m multi-rack scale-up reach as five contenders: dielectric RF/microwave cables, slow-and-wide VCSEL arrays, slow-and-wide DWDM, fast-and-narrow optics with advanced packaging, and 400G-PAM4 DR8 + BiDi. We broke down this map in full in Seven Paths for Scale-Up Optical Interconnect; at ECOC, each camp effectively filled in the numbers.
4. The Fast & Narrow camp: XPO pushes pluggables to the limit, CPO is already shipping
4.1 XPO: one module replaces 8 OSFPs
Andy Bechtolsheim began by acknowledging that OSFP is the highest-volume pluggable ever: more than 120 million units shipping this year, projected to exceed 200 million in 2028. But the bottleneck is clear: at most 32 ports per 1U, and a per-module power ceiling of 30–40 W.
XPO (eXtra-dense Pluggable Optics) solves this by scaling the pluggable up as a whole:
One XPO = 12.8T, with 64 × 200G channels: two 32-channel paddle cards sandwich a shared liquid-cooled cold plate back to back, giving roughly 4x the front-panel density of OSFP.
A 204.8T switch fits in 1U with 16 XPOs; with OSFP it takes 128 modules and 4U.
For 512 XPUs at 25.6T of scale-up bandwidth each, the OSFP approach needs 8 switch racks (more than the GPU racks), while XPO needs only 2.
The timeline is set: the XPO MSA was founded on March 20, 2026 and now has 150 members (Andy called it "the largest optics MSA ever"); the 1.0 spec was released on July 31; production modules are expected to ship in Q1 2027, ramping around late 2027 to January 2028, with a 204.8T switch as the launch platform.
The biggest news was 400G/lane. Arista is working with Foxconn Interconnect Technology (a Foxconn subsidiary) to simulate a 448G card-edge connector: today's 224G connector's insertion loss collapses at about 90 GHz, while the 448G version holds up to about 125 GHz, with the first measured results expected in October. The 25.6T XPO thermal design can handle 500 W and fit full C/O-band transceivers into a single module.
Andy's conclusion: "200G → 400G SerDes will dominate the next generation." That is exactly XPO's bet.
4.2 CPO: Broadcom's and NVIDIA's answer is reliability
Broadcom's Rajiv Pancholy distilled CPO's value to one thing: reliability.
Tomahawk 6-Davisson is the industry's first 102.4T CPO Ethernet switch, using 70% less power than pluggables, with 10x better reliability and more than 1 million cumulative hours without a link flap.
Citing Meta's ECOC paper from last year: on a 24K cluster, CPO improved training-job efficiency by about 90%. The reason: every link flap forces a rollback to the last checkpoint — one bad link takes the whole cluster down with it.
CPO roadmap: TH4 Humboldt (2022, 25.6T) → TH5 Bailly (2024, 51.2T) → TH6 Davisson (2026, 102.4T, 200G/lane) → 4th-gen CPO (2028).
NVIDIA's numbers were even harder: the Spectrum-6 CPO switch delivers 102.4 Tb/s from 512 × 200G ports and 32 × 3.2T CPO engines, at under 4 pJ/bit including the laser — 3.5x more efficient than fully retimed pluggables. The engine uses TSMC COUPE: the EIC on a FinFET logic process and the PIC on SOI N65 silicon photonics, bonded with SoIC, with micro-ring modulators and µLens grating couplers; the 212.5 Gbps links in production run at BER below 1e-10.
When someone on the panel asked NVIDIA directly about XPO, Ling Liao answered in one line: "We are fully committed to CPO."
5. The Slow & Wide camp: OCI is the standard, DWDM is the weapon
5.1 OCI MSA: decoupling electrical and optical with NRZ
The OCI MSA (Optical Compute Interconnect) was founded in March 2026; its founding members are Meta, Microsoft, OpenAI, AMD, Broadcom and NVIDIA. Broadcom used one table to explain why it's needed: a 200G PAM4 electrical interface can be linear, 400G maybe, and 800G is "unlikely." So OCI simply decouples electrical from optical:
Gen1 = 4 wavelengths × 50G NRZ, bidirectional, 200G per fiber; the next generation moves to 100G NRZ, then stacks wavelengths with DWDM, theoretically growing all the way to 3.2T.
Broadcom modeled a single-tier scale-up cluster of 1,024 XPUs: 25.6 Tbps per XPU, 204.8T switches, 16 GPU racks plus 4 switch racks in total; each GPU needs 128 BiDi fibers, and each switch rack needs 32,768 fibers. Today's NVL is 72 or 144 GPUs.
Microsoft's Fotini Karinou was candid about OCI's timeline: 200G is today, 400G is marked "2027(?)", and 800G "TBD, >2030(?)". The question marks were on her own slides. Someone in the audience pressed: 4 × 50G can barely stretch to 4 × 100G — how do you get to 4 × 200G? The answer was more wavelengths and higher baud rate. Sounds reasonable, but there's no data to back it yet.
Microsoft's rollout comes in two waves: Wave 1 uses off-package optics for scale-up on OCI Gen1; Wave 2 moves to CPO-level integration while extending optics to CPU PCIe/CXL memory pooling. The specs for the latter are tough: optical module latency <5 ns, <4 pJ/bit, and reach extending from 1–3 m within a rack today to 20–50 m across a whole row — and VCSELs have a shot here.
5.2 DWDM and VCSEL: the numbers are no longer just slideware
Although NVIDIA bets on CPO for scale-out, its main R&D direction for scale-up is actually DWDM NRZ. The live demo: 8 wavelengths at 32G each, 256G per fiber, 200 GHz spacing, spacing error ±20 GHz, power variation ±0.5 dB, SMSR about 60 dB, all channels locked for 16 hours with zero errors, and eye timing margin close to 0.5 UI. For lasers there are three paths: individual ultra-high-power lasers, laser arrays plus a MUX, or comb lasers. Ling Liao said "there's no one-size-fits-all winner" — it depends on product timing, per-wavelength power and wavelength count.
Corning's Chris Wu cited Broadcom's data: a 100G VCSEL 3.2T NPO draws 5.3 W, or 1.5 pJ/bit, versus 5–9 pJ/bit for SiPh CPO/NPO; reliability is <0.1 FIT, and 18 NPOs give an XPU 58T of escape bandwidth. The cost is fiber: each NPO needs 4 MPO-16s. Corning's answer is a fiber bundle that packs 64 fibers into one connector, cutting the connector count to a quarter. But he admitted the bundle only supports multimode today — single-mode isn't ready yet.
6. The real battlefield: a pJ/bit ruler and a gearbox tax
Line up every vendor's published pJ/bit on a single ruler and you can see where each camp is stuck.
The key is Arista's two architecture diagrams. Slow-and-wide optics are very efficient on their own — 8 × 50G NRZ VCSEL needs only 1 pJ/bit — but the XPU emits 400G PAM4, so the signal must first pass through an 8:1 inverse gearbox, which alone eats 4 pJ/bit. The DWDM version is the same: a 4:1 gearbox also costs 4 pJ/bit. Most of the power the optics save is eaten back by the gearbox.
TeraHop's Ryan Yu (co-chair of both the XPO and Open CPX MSAs) made the same point with a bar chart: as long as the XPU must support both copper and optics, it has to keep 200G-PAM4 SerDes; under that constraint, Open CPX NPO with an integrated laser can reach <5.6 pJ/bit, the most practical answer. Slow-and-wide has to wait until "some year" when SerDes is truly removed before its power drops into the low single digits.
Slow-and-wide isn't losing on optics — it's losing on timing: the XPU's I/O isn't ready to be redesigned for it.
imec takes the opposite view: DSPs and high-speed data converters make it very hard to get below 1 pJ/bit, and future systems must get there, so the only path is very simple NRZ optical lanes, with packaging and integration restoring the bandwidth. Both sides are right; the only difference is the year.
7. Lasers: integrated or external? Dust is the No. 1 killer
Scintil's Sylvie Menezo laid out the specs for a scale-up external laser source (ELS) clearly: 200 mW of optical power per wavelength, >10% wall-plug efficiency at the fiber, RIN < -144 dBc/Hz, 1 MHz linewidth, wavelength spacing shrinking from 20 nm all the way to 0.57 nm, ±0.2 nm grid accuracy — and manufacturable at a scale of 1 billion units. Her assessment: only discrete InP DFBs meet the bar today, but conventional 4-inch InP processing requires per-device gratings, bar cleaving, facet coating and active alignment, so volume can't scale.
Scintil's approach keeps the DFB but builds the grating on 8-inch silicon wafers, with III-V providing only gain: 16-laser arrays are tested at wafer level, and only one active alignment is needed per 8/16 lasers. Progress: a 400 µm cavity delivers 50 mW (50°C) and 16% WPE today; a 1300 µm cavity targets 100 mW (December 2026); a 2000 µm cavity targets 200 mW (Q3 2027).
The panel debate on laser reliability was a highlight. TeraHop brought data: more than 25 million SiPh transceivers shipped and over 100 billion device-hours, with PIC FIT <0.01, so it argues lasers should be integrated. NVIDIA's response: CW lasers are indeed reliable, but CPO demands maximum density, so anything that can be moved out should be moved out — external placement also makes servicing easier.
In the end the room reached a rare consensus: the most common failure is dust, followed by human handling during plugging. Andy noted that when a pluggable fails, you pull it and send it back to the vendor; in an integrated solution, the same dirty connector triggers a "witch hunt." Cerebras' JP Fricker put it most directly: "Whoever reduces the number of dusty interfaces wins." Further reading: Fiber-to-Chip: The Least Sexy Step in CPO That's Blocking Everyone.
8. One step further: optics grown directly into the wafer
In the second half, two speakers pushed the timeline beyond 2030.
imec's 3D optical I/O: the XPU is stacked on an optical interposer via Cu-Cu hybrid bonding, running 32G/64G NRZ with no DSP and 32–64 wavelengths to restore bandwidth. GeSi EAMs plus 2 nm CMOS target 0.5 pJ/bit; switching to III-V EAMs plus GaAs quantum-dot lasers, the target is 0.25 pJ/bit, 16 Tb/s/mm, and 330 mm reach. That spec is a full two orders of magnitude beyond today's electrical interconnect.
Cerebras' wafer-scale optical I/O: the WSE's on-chip memory bandwidth reaches 43,200 TB/s (NVIDIA Rubin is 22 TB/s). The CS-6 announced at Hot Chips 2026 will stack DRAM wafers via hybrid bonding; the next step is stacking an optical wafer, so that optical-electrical conversion happens directly above any compute region on the wafer surface — optical bandwidth then scales with wafer area, not just its perimeter. One contrast is worth noting, though: Cerebras' current systems have actually moved back from near-package optics to pluggable optics, citing modularity and serviceability.
Tyndall's Peter O'Brien filled in the packaging side: a glass substrate fits 64 packages on a 200 mm wafer, versus 644 on a 510 mm panel. But the glass core is packed with electrical vias, leaving almost no routing room for optical waveguides, so they build the optics on top of the glass instead.
9. Timeline: 2027 is the year pluggables are pushed to the limit
Stack all the timelines together and the rhythm is clear:
2026–2027: XPO 1.0 spec, Open CPX Rev 1.0 (released September 16, with about 46 companies joined and about 40 more under review), and XPO modules in volume production in Q1 2027. Fast-and-narrow pluggables and NPO go first.
2028: the first 400G SerDes switch chips, Broadcom's 4th-gen CPO, and the XPO ramp. Fast-and-narrow moves up another notch this year, making slow-and-wide's gearbox tax hurt even more.
2029–2030: TeraHop estimates slow-and-wide volume production lands in this window, with 2027–2028 for proof-of-concept and limited deployment. OCI 800G comes after 2030.
As we noted in our LightCounting CPO/NPO conference recap, the industry's focus has shifted from "does the technology work" to "who can reliably ship millions of units." This ECOC adds another dimension: who can wait until the XPU redesigns its I/O for them.
10. What it means for Taiwan's supply chain
The 2027–2028 money is on the fast-and-narrow side. XPO makes a single module's value equal to 8 OSFPs plus a liquid-cooled cold plate, raising the bar for both assembly and liquid cooling. Foxconn's FIT is a core founding member of XPO and co-developed the 448G card-edge connector with Arista; Open CPX's early contributor list includes Accton and Lotes. Connectors, liquid-cooling quick disconnects and switch ODMs are the first links to benefit from this wave.
CPO packaging leadership clearly sits with TSMC. NVIDIA's CPO engine explicitly specifies TSMC COUPE (N65 SOI PIC + FinFET EIC + SoIC). For Taiwan's OSATs and test houses, the opportunity lies in the three bottlenecks Broadcom named: connecting more than 1,000 fibers to every package, detachable fiber connectors, and automated assembly and test.
Lasers are something both camps need. Fast-and-narrow needs CW lasers to feed SiPh; slow-and-wide needs multi-wavelength DFB arrays or comb sources — and Scintil is talking about demand on the order of "1 billion units." InP epitaxy and CW DFB laser makers (such as LandMark Optoelectronics) still benefit, but specs will shift from "single high-power device" to "multi-wavelength, narrow spacing, wafer-level testable." Whoever first delivers a 100–200 mW DWDM source with ±0.2 nm wavelength accuracy catches the 2029 train.
VCSELs are back in play for scale-up and CXL memory pooling. 1.5 pJ/bit, <0.1 FIT, plus consumer-electronics-scale volume — provided multimode fiber bundles and connectors keep up. Taiwan's VCSEL epitaxy and device makers can start tracking Microsoft's Wave 2 timeline.
Conclusion
The most valuable thing about this Symposium is that it dismantled the false debate of "CPO vs pluggable." XPO is itself a pluggable, Open CPX supports both NPO and CPO, NVIDIA bets on CPO for scale-out while researching DWDM for scale-up, and Cerebras even went back to pluggables. Packaging format is just the outcome; the real variable is where the SerDes at the XPU edge goes.
If 400G PAM4 SerDes reaches volume production on schedule in 2028, fast-and-narrow gets another three years, with XPO winning on serviceability and CPO on reliability.
If XPU makers start offering native low-speed parallel I/O for scale-up (AMD, NVIDIA and Broadcom are all OCI founding members), slow-and-wide's gearbox tax drops to zero overnight, and the pJ/bit gap jumps from 5x to more than 10x in one step.
Three signals to watch next: Arista's October measurements of the 448G card-edge connector, whether the question marks come off the OCI Gen2 400G spec timeline, and whether Scintil's 200 mW DFB ships in Q3 2027. The first decides how long fast-and-narrow lasts; the other two decide when slow-and-wide takes over.
Related reading
OIF Draws the Official Map for AI Interconnect: Three Networks, One pJ/bit Battlefield: read this first to understand why pJ/bit is the main battlefield
CPO Roadmaps by Player: Beyond the Big Four, a Whole Line of Challengers: how Broadcom, NVIDIA and Marvell are positioned on CPO
This article is for technology and industry trend analysis only and does not constitute investment advice.
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