After Copper Gives Out for AI: Seven Paths for Scale-Up Optical Interconnect, and Two Ways to Live With the Bottlenecks

AI training has pushed in-rack (scale-up) optical interconnect demand to 7–10x that of scale-out, and copper is the first thing to give out. There are a dozen-plus solutions on the market, but at bottom there are only two philosophies for assembling bandwidth: Fast-and-Narrow (few lanes, high per-lane rates, PAM4 plus heavy DSP) and Slow-and-Wide (many lanes, moderate rates, NRZ, minimal DSP). All seven major approaches choose a point along this axis, and each path hits a symmetric wall. This article first lays out the "why" and the yardstick; the vendor-by-vendor breakdown and full analysis of the two walls are in the premium section.

1. Why now: scale-up has forced optics into the rack

Optical modules used to fight mainly in scale-out: east-west traffic between racks, won by pluggable modules with DSPs. AI moved the battlefield. Training binds tens of thousands of GPUs into one logical machine, so in-rack (scale-up, the NVLink layer) interconnect density has exploded; the industry estimates its volume at 7–10x scale-out. This layer used to be copper's territory, but as per-GPU I/O races toward 1.6T and 3.2T, copper's reach shrinks sharply at high speed, making it impossible to connect more GPUs within a rack. So optics are being pushed right up next to the ASIC, and NPO and CPO suddenly became the hot topic. Not because of a technical breakthrough, but because copper can't keep up.

2. One yardstick for the whole picture: Fast-and-Narrow vs Slow-and-Wide

Remember one equation: bandwidth = per-lane rate × number of lanes. There are two ways to reach 3.2T: Fast-and-Narrow uses few lanes, each pushing 200–400G, relying on PAM4 and aggressive DSP; Slow-and-Wide uses many moderate-speed lanes running clean NRZ, cutting the DSP back or removing it entirely. FaN puts the cost burden on the circuitry (DSP power, thermals, linearity); WaS puts it on lane count (area, fiber bundles, component count). The most common mistake: "which material" and "FaN or WaS" are two independent dimensions. The same VCSEL or the same silicon microring can go fast-and-narrow or slow-and-wide, so you can't label them with a single phrase.

3. How far the optical engine sits from the ASIC: another, orthogonal axis

Before choosing a light source, look at where the optical engine sits. The closer it is to the ASIC, the shorter the electrical channel, the lower the power and the higher the density, but the harder it is to service. That's the difference across Pluggable → LPO → NPO → CPO. NPO's value isn't being the most power-efficient; it's being "efficient enough while still serviceable" (the socket is replaceable), which is why it's seen as the most practical transitional form before CPO goes mainstream.

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That's the summary of this article: why copper can't keep up, and the yardstick for the whole picture (Fast-and-Narrow vs Slow-and-Wide, and how far the optical engine sits from the ASIC).

STT's full analysis is in the premium section: each of the seven approaches (VCSEL, SiPh MRM, SiPh MZM, TFLN, EML/InP, microLED, optical I/O chiplets) with its progress and Achilles' heel, the DSP wall at 200G and the VCSEL wavelength civil war, the full technology stack NVIDIA has endorsed for slow-and-wide, and two underrated supply chain nodes in InP and SiPh wafers.

👉 Subscribe to the STT premium section and read the full analysis on vocus (in Chinese): https://vocus.cc/article/6a69689efd89780001b725d9

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