OFC 2026 - Breaking the GPU Cluster Scaling Bottleneck: A 1060nm Sensing-Grade VCSEL Interconnect - Lumentum Operations LLC

2 days ago

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Introduction

As discussed at OFC 2026, the frantic buildout of AI compute infrastructure has pushed the global optical component supply chain into unprecedented tightness, from isolators and indium phosphide (InP) materials to conventional pluggable modules. To address the increasingly demanding scale-up challenge of multi-rack GPU clusters, Lumentum (also rendered as "Connective" in the transcript) CTO Matt Cusack proposed a very different path: a high-density interconnect built on 1060nm gallium arsenide (GaAs) sensing-grade VCSEL arrays. The approach is designed to sidestep the costly high-speed InP material bottleneck and directly leverage the mature 3D sensing manufacturing capacity of consumer electronics and automotive, creating a low-power, low-cost and highly flexible short-reach interconnect architecture.

Core Technology and Data Deep Dive

Squeezed by GPU bandwidth doubling every generation and soaring power density, conventional ultra-high-speed serial links face power and yield bottlenecks. Lumentum's strategy is "slower lanes, more lanes," raising total bandwidth through high-density arrays.

The Strategic Shift from 850nm to 1060nm

Conventional 850nm VCSELs and fiber have been tightly bound to specific wavelength standards.
The 1060nm substrate is transparent, enabling ultra-high-density 2D emitter and detector arrays.
It supports flip-chip packaging, significantly improving signal integrity and back-end manufacturability.
Building on know-how from the 980nm LiDAR era, 1060nm VCSELs operate above 125°C with very high reliability, fitting seamlessly into the hot thermal environment around GPUs.

Key Metrics

Up to 32 Tbps of bidirectional bandwidth in a physical package footprint of just 8x8 mm.
End-to-end total power below 2.5 pJ/bit, including all components: die-to-die interface, TIA (transimpedance amplifier), driver and CDR.
Shoreline density exceeds 4 Tbps/mm, using relatively simple NRZ modulation.
Excellent bit error rate (BER), well below 10^-12.
Each lane currently runs at 32 Gbps, but 1060nm material offers higher differential gain, giving it the physical headroom to scale to 64 Gbps or even 200 Gbps.

Supply Chain and Market Impact

A Mature Supply Chain Changes the Game

This architecture directly taps the massive 3D sensing VCSEL capacity built up for Face ID and LiDAR, fully addressing the capacity and yield bottlenecks of high-speed optical materials.
Module packaging is fully compatible with standard surface-mount technology (SMT), avoiding complex high-temperature fiber alignment and significantly lowering final assembly cost.
On the fiber side, Lumentum is working closely with Corning on an 80-fiber multimode fiber array and a custom hex-arrangement connector; micron-level alignment accuracy ensures stable high-channel-count interconnect and effectively amortizes fiber termination cost.

Simple Tech Trend View

Silicon photonics (SiPh) has long-term advantages in density and integration, but still faces sizable challenges in system-level power and initial deployment cost for GPU scale-up networks. Lumentum's 80 Tbps integrated VCSEL+ASIC concept tray shown at the event makes a strong case for "mature materials + new architecture."

We expect that over the next 12-24 months, as IEEE advances standardization of 200G 1060nm VCSELs, sensing-grade VCSEL solutions built on the mature GaAs supply chain will, thanks to very low power (<2.5 pJ/bit) and massive capacity, become a strong alternative for short-reach in-rack server interconnect and even for next-generation CPO (Co-Packaged Optics).