OFC 2026 - Advanced Silicon Photonics Packaging Interconnects: The Last Mile of AI Inference Architecture - GlobalFoundries
In 2026, as AI compute demand explodes, the "last mile" between fiber and chip has become the performance bottleneck of compute interconnects. At an OFC 2026 technical forum, GlobalFoundries (GF) foundry technology architect Kevin Dezfulian, speaking on AI inference solutions, laid out why silicon photonics (SiPh) packaging is inevitably shifting from "permanently attached" to "detachable" interconnects. The talk not only revealed GF's progress in CPO (co-packaged optics), but also pinpointed the core challenges of test and high-volume metrology in 2.5D/3D integration.
Silicon Photonics Packaging Evolution: From PIC to Optoelectronic (OE) Interposer
GF simplifies today's packaging formats into four evolutionary stages - essential for understanding future GPU/NPU integration paths:
PIC Face-Up (Wire Bond): Traditional wire-bonded packaging - mature, but bandwidth-limited.
CPO / GPU integration: Uses TSV (through-silicon via) for 3D stacking, letting the PIC act directly as an optical interposer.
Active optical interposer: Relies on monolithic photonics, placing multiple heterogeneously integrated electrical dies on top of the PIC so computation happens directly on the PIC.
Passive OE interposer: For large chips exceeding one reticle in width, routing both optical and electrical signals on a silicon substrate.
The Key Inflection: Why Detachable Fiber Is a Must-Have in the 1.6T Era
Today's market benchmark is Direct Attach technology, typically with a fiber pitch of 127µm or 250µm, and it has passed stringent reliability testing. But GF pointed out its fatal flaw: when CPO needs to support high-density designs with more than 100 fibers, permanently attached pigtails make package assembly costs unacceptable.
To overcome this, GF proposed two technology paths:
1. GlassBridge (with Corning)
Using patterned glass, it adapts the standard V-groove structure to standard fiber connectors. This greatly simplifies assembly, with low insertion loss and low polarization mode dispersion (PMD).
2. Mode Expansion & Collimation
Facing the physical mismatch between a waveguide mode of only 1µm and packaging tolerances of 5-20µm, GF uses mode expansion and collimation to relax alignment sensitivity.
Turning mirror: Grating couplers are bandwidth-limited in the O-band and have higher polarization-dependent loss (PDL); GF instead favors a turning-mirror approach with micro-optics embedded in a micro-optic cavity, delivering more stable broadband performance.
Ecosystem Data Face-Off: Teramount vs. Senko
GF disclosed the latest measured data from two key partners:
Terabaud (Teramount solution): A pluggable micro-optics design whose core advantage is Wide Acceptance Optics, removing the need for extremely precise alignment in package design. It is being demoed live at the GF booth.
Senko detachable connector: The first time GF has publicly shared this data. Senko's approach uses active alignment to locate the optical signal at the package level; measurements show lower loss and very high repeatability across multiple mating cycles (loopbacks).
Manufacturing and Test: Challenges from Wafer Level to OE Die Sort
Dezfulian stressed that silicon photonics test has "started" but is not yet "mature." To secure volume yield, GF has introduced multi-level inspection:
Inline metrology: Using confocal microscopy and 2D/3D inspection systems to monitor complex 3D structures in real time.
Advanced test probes: Using periscope optical probes to inspect structures after micro-assembly.
OE Die Sort: To produce known-good die (KGD), GF is building a system that requires simultaneous front-side and back-side probing - very challenging in practice.
Simple Tech Trend View: Packaging Is the Moat of the Future
GF is building a complete packaging and assembly flow in the US, covering wafer test, processing and final deployable units. The signal is strong: in silicon photonics, foundry wafer services alone are no longer enough - vertically integrated packaging and test (OSAT) capability is what will decide market share in 1.6T-and-beyond optical modules.
We expect detachable connectors (such as the Senko or Teramount solutions) to enter large-scale validation in AI inference servers within the next 12 months. Once the yield bottleneck is broken, fiber will no longer be a burden on the PCB, but a standard component as flexible as pluggable memory.
Comments