2026 OCP APAC Summit | Ayar Labs | Mark Wade | Demand Needs 10x, Supply Gives 2x: The 5x Gap Pushing Optical Interconnect Onstage

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Ayar Labs CEO Mark Wade spent no time at OCP APAC arguing that “optics beats copper.” He opened with arithmetic: if token demand grows 10x a year, while new power capacity grows only 1.4x a year and per-chip silicon performance also only 1.4x, the two multiply to 2x. The gap in between, 5x every year, compounding year over year, can only be filled by system architecture. In this framing, optical interconnect isn’t “a better cable”; it is the only variable that lets rack architecture be redesigned.

And the line from this talk that truly deserves to be remembered isn’t about CPO. It’s this: once all high-speed connections leaving a chassis go optical, the unit of adoption drops from “a whole rack” to “a single chassis”. That sentence decides which layer Taiwan’s supply chain will make money in over the next three years.

1. Start with the 5x gap

Wade’s current-state numbers: global monthly token output has reached roughly 35 quadrillion, up about 160x over the past two years. That volume isn’t driven by chatbots. He said plainly it’s “no longer just you or me sending ChatGPT one message and getting one reply.” It’s driven by agents.

Then he did what most keynotes don’t dare to: he laid out the supply side.

Item: Token demand (scenario assumption); Annual growth: 10x/year, 10,000x cumulative over four years

Item: New US AI data center power; Annual growth: ~1.4x/year

Item: GPU/accelerator silicon performance and throughput; Annual growth: ~1.4x/year

Item: Total supply side; Annual growth: ~2x/year

Item: The gap; Annual growth: ~5x/year, compounding

He admitted the 10x line “isn’t a confident forecast”; it simply spells out what it would take to sustain that kind of growth. But the point isn’t whether that line is accurate. It’s that the two 1.4x figures in the denominator have physical ceilings: power build-out is limited by the grid and land, and per-chip gains are limited by process technology and the power bottleneck. Neither number is going to suddenly become 3x anytime soon.

So the gap can only be closed from a third place: architecture. Optical interconnect is being pushed onstage not because it’s sexy, but because every other road is blocked.

2. Agentic AI splits one workload into four pieces

Wade split the agentic workload into two halves, and the cut is worth noting.

The inference side runs on GPUs/accelerators and has already split internally into prefill (compute-bound) and decode (memory-bound), with hardware specialization already underway. The tool-calling side runs compiled code on general-purpose CPUs, behaving more like a CPU shuttling data between memory and storage.

A single agent task runs this loop hundreds to thousands of times. That is the mechanism behind the token explosion, and it’s why dedicated CPU racks are starting to appear at OCP. We saw the same signal in our breakdown of AMD’s keynote: the CPU-to-GPU ratio is converging from 1:4 toward 1:1.

Once you accept that the workload splits into four pieces, each wanting its own dedicated hardware, you’re forced toward a composable system: different chassis each optimized on their own, then stitched together with high-performance interconnect. And that “stitching” can’t be done in a copper world. That’s where the argument closes.

3. Optics’ value isn’t saving power; it lifts the entire trade-off curve

For the system-model chart Wade showed, the two axes matter more than the chart itself:

X axis: interactivity (tokens/sec/user), where the “user” is increasingly an agent. He stressed that humans are limited by reading speed, so the tokens they can digest are capped; agents have no cap and consume as fast as the hardware can produce. Further right is better.
Y axis: throughput at fixed power, because new power capacity is the hardest ceiling.

The key point: for a given architecture, you can only slide along that curve. More interactivity costs throughput, and vice versa. You’re locked onto the line.

What optical interconnect does is switch to a different curve: starting from a baseline 128-GPU electrically connected scale-up domain, pulling optics directly from the XPU into the scale-up fabric shifts the whole curve up and to the right once; attaching optically connected memory and storage appliances shifts it again. His words were “step changes in multiples,” not incremental gains.

This is the same idea as what Astera Labs said at the same event, told two ways: the value of optics isn’t a pretty energy-per-bit number; it’s that it unlocks the physical boundary of the pod, opening room to redesign topology and radix.

4. The line to remember: the unit of adoption drops from rack to chassis

Inside today’s racks, connections are electrical, and electrical links carry a hard bandwidth-distance trade-off. That trade-off forces a whole chain: components must be packed tightly → per-rack power density soars → chassis, cooling, and rack design all become expensive and custom → facility power and cooling are pushed to the limit → in the end only a handful of players can build the whole thing, and the supply chain becomes a closed, locked-in proprietary system.

Wade laid out this causal chain bluntly, then offered the alternative: convert every high-speed connection leaving the chassis to optics. Do that, and the “unit of adoption” falls from “a full rack-scale system” to “a single chassis.” In his words, my unit of simplicity becomes “I want to connect a bunch of chassis together.”

This matters far more than it sounds. Buyers no longer have to swallow an entire proprietary rack design at once; they can mix and match chassis from different vendors. Cooling and power inside each chassis can be optimized independently, without cramming everything together to accommodate electrical signal reach. And GPUs, accelerators, switches, and memory/storage can share the same physical framework. Wade said explicitly that the chassis reference design “isn’t GPU-only”; optical connections exiting the bottom of the chassis work for all four device types.

This is exactly why OCP exists: to open up what is closed. Bringing optical interconnect into the chassis aligns squarely with OCP’s mission.

5. Hard evidence: Wiwynn’s chassis, Alchip’s back end, COUPE’s front end

What Wade showed onstage were photos of real hardware, not renders. Three Taiwanese partners each hold one segment.

Wiwynn: chassis and rack. The partnership was announced in March 2026. Public information shows an L10 chassis/L11 rack integrating CPO and liquid cooling, supporting up to 32 compute trays and 64 AI ASICs per rack, with a 16-rack cluster able to support 1,024+ accelerators. Wade noted onstage that the design has moved into an ORv3-style rack concept, with more public demos coming from the second half of this year into next year.

Alchip: back-end ASIC integration. Once optical engines can be produced reliably on high-volume CMOS lines, they need to flow into back-end ASIC integration services so customers have something they can architect around. The two companies have already demonstrated the industry’s first optical connectivity solution based on TSMC COUPE.

TSMC COUPE: front-end optical engine. Here’s an easily overlooked point: Wade believes COUPE’s biggest contribution isn’t the process itself, but that it defines a de facto set of optical-engine-level physical interfaces. Once that interface stabilizes at the foundry, downstream connector makers, assemblers, and OSATs finally have a stable target to aim at and the confidence to invest in capacity.

This section dovetails with TSMC’s 3DIC talk at the same event: advanced packaging is becoming the gatekeeper of AI compute, and signaling will be handed to optics.

6. The definition of CPO is loosening

The industry changes how it talks about “dense packaged optics” three times a year, and the definitions of CPO, NPO, and XPO conflict with each other. Wade offered the cleanest definition so far, which he credited to a peer at Google:

Think of co-packaged optics as “optical engines assembled onto a substrate,” and then you put that substrate wherever you want.

This definition decouples the “technology” from the “form factor.” Ayar Labs positions itself as a designer and manufacturer of high-performance optical engines. Yes, their focus with a lead customer is integrating optical engines directly into GPU and accelerator packages, but the same optical engine can become an on-board NPO module, go onto an interposer (which they did a few years ago), or become a high-density pluggable. Wade himself noted this is similar thinking to the XPO shown by Arista at the same event.

For Taiwan’s supply chain, this is an important signal: the binary narrative of “CPO wins, pluggables die” is wrong. What’s actually happening is optical engine standardization and diversification of packaging form factors. Makers of connectors, FAUs, fiber arrays, and substrates are serving multiple shells around the same optical engine.

As for the light source, Wade placed external laser sourcing alongside tightly integrated optical engines as a “viable path to manufacturable CPO.” Why this is the most fragile link, we broke down in The most fragile link in CPO is the laser: silicon’s original sin is that it can’t emit light, and lasers hate heat yet are asked to sit next to the heat source.

7. Standards positioning: a seat at all three tables

Wade devoted an entire slide to “what should be standardized and what shouldn’t.” That’s the best indicator of whether a CPO company is serious about volume production.

At the protocol layer, they are an NVLink Fusion optical partner, while also looking at Ethernet, ESUN, and UALink over Ethernet. Onstage he directly acknowledged NVIDIA’s Gilad Shainer from the previous session, saying customers can swap in different optical connectivity and still tap that protocol ecosystem (see our piece on Gilad Shainer’s open networking keynote). Die-to-die uses UCIe. At the optical engine layer they back the OCI MSA, the optical scale-up specification alliance launched in March 2026 by six founding members (AMD, Broadcom, Meta, Microsoft, NVIDIA, and OpenAI), targeting 3.2 Tb/s per lane. Optical connectors are all industry-standard parts, with an unambiguous principle: to let chassis scale in volume, use off-the-shelf standard components wherever possible.

A startup sitting in both NVLink Fusion and the OCI MSA, betting on TSMC COUPE, and using standard connectors sends a single message: they’re wagering that “open interfaces + diverse form factors” will beat “a single closed solution”.

8. How slow and how wide is “slow and wide”?

The Q&A had just one question, but it was high-value. Someone asked: AI inference demands extremely low latency, so is slow and wide a better fit?

Wade first corrected the premise: The term has been overused; some people take it all the way down to 1 Gbps per lane. What Ayar Labs means by slow and wide is 50 to 100 Gbps NRZ per wavelength.

He then gave a full latency breakdown. Low latency comes from three places: the die-to-die interconnect itself must be low-latency; serialization on the high-speed data path must be low-latency; and the optical link must operate in a good native error-rate regime, so you can use a lightweight, low-latency error-correction architecture instead of paying the latency cost of heavy FEC.

That’s the core reason for choosing NRZ over PAM-4: NRZ’s native BER is much better, which greatly simplifies the entire error-correction architecture. In a latency-sensitive network like scale-up, FEC latency matters far more than a few extra Gbps per lane. For Taiwanese companies doing DSP, TIA/driver, and test, this is a concrete signal: the spec trade-offs for scale-up optical interconnect are diverging from scale-out pluggables’ long-standing pursuit of maximum per-lane speed.

9. The counterargument: what if “copper vs. optics is a false dichotomy” is right?

To be fair: at the same summit, SemiAnalysis’s Dan Nishball called the copper-vs-optics fight in scale-up a false dichotomy. In his view the real inflection is HBM de-specing freeing up budget for scale-up networking, with copper holding inside the rack and optics filling in across racks, both pushed into volume together.

This doesn’t fully contradict Wade’s narrative, but it would change the timeline. If copper can hold inside the rack for another two or three generations, “the unit of adoption shrinking to the chassis” gets pushed out, and every supply-chain name betting on CPO ramping in 2027 would first have to endure a painful stretch where valuations and shipments decouple.

There are three other risks Wade himself didn’t dodge: thermal management (with the optical engine next to the package, the laser reliability ceiling is pushed down), yield (optical engine attach yield is a shared pain point; it was the one concern Arista’s Bechtolsheim raised about CPO at the same event), and serviceability (when a pluggable fails you swap the module; when CPO fails you lose the whole package). Until this last hurdle is cleared, hyperscalers won’t bet an entire rack on it.

So my read is: the direction is almost beyond dispute; the timing is the variable. Wade himself has pointed elsewhere to 2028–2029 for CPO scale-up volume, not next year.

10. Conclusion

The most valuable part of this talk isn’t “CPO matters” (that’s three-year-old news); it’s that he reduced the necessity of optical interconnect from a technology preference to an arithmetic problem: demand grows 10x, supply 2x, and the 5x in between can only come from architecture.

For Taiwan’s supply chain, three things are worth changing now.

First, shift from “selling components” to “selling a chassis layer.” The unit of adoption dropping from rack to chassis determines who is a system partner and who is a parts supplier. Wiwynn already occupies that position: chassis, rack, ORv3, liquid cooling, and CPO integration form a complete layer, not a single part. Everyone else should ask: inside that chassis, am I selling a replaceable part, or a spec-locked interface?

Second, watch the physical interface that COUPE defines. Once the foundry pins down the optical engine’s physical interface, downstream connectors, assembly, and test will finally dare to invest. The day that spec goes public is the starting gun for Taiwan’s back-end players.

Third, stop making decisions in a “CPO vs. pluggable” either-or framework. The same optical engine will wear four shells: CPO, NPO, interposer, and high-density pluggable. Bet on the wrong shell and you die; betting on the right engine is what matters.

On timing I remain conservative: 2026 to 2027 are the years of reference designs, samples, and spec finalization; real volume lands after 2028. Any name priced on “CPO explodes next year” will get corrected by time first.

This article is for technology and industry trend analysis only and does not constitute investment advice.