At VLSI 2026, Intel showed a fully working silicon photonics microring DWDM transceiver: 16 wavelengths at 50Gb/s each for 800Gb/s per fiber, all with BER<1e-9, at about 5.7pJ/b, with 22nm CMOS stacked directly on the photonic chip in an open-cavity package. We break down this device-to-system CPO reference design figure by figure.

NVIDIA proposes a symmetrical, wavelength-agnostic bidirectional silicon photonics link that uses polarization multiplexing to break CPO's port-count and cost bottlenecks. Error-free 32 Gbps bidirectional operation makes "colorless" optics a reality and paves the way for scaling AI cluster networks.

Silicon photonics gets the spotlight, but Intel's 0.9 pJ/b 108G PAM4 link shows VCSELs remain an underrated low-power path for short-reach CPO. We walk through this CICC 2026 paper section by section, figure by figure, and identify the last three miles VCSEL CPO must cover to reach volume: equalization, packaging and thermals.

Keio University's "Mosquito method" draws light paths into polymer with a single needle, using a graded-index core to avoid interface scattering for near-material-limit loss — and uses fluid dynamics to beat the needle-size limit for 20 µm pitch. What is the open question for the polymer waveguide route?

CPO volume production is held back by micro-lens pick-and-place and active alignment. AIST turns the lens-mirror into an opto-chiplet embedded during molding, routes light with an Optical RDL, and widens alignment tolerance to ±12 µm.

AIST × KYOCERA have lit up the long-shelved AOP concept for the first time: an embedded SiPh chip, polymer ORDL and 3D micro-mirrors deliver 112 Gbps PAM4 with 3.35 dB TDECQ, passing IEEE specs. How far has the polymer optical-redistribution route come?

Qnity builds optical waveguides into the PCB process with BCB dry film: the lowest adoption barrier, 0.07–0.11 dB/cm loss, and it survives reflow and high temperature/high humidity. It also honestly debunks the common assumption that widely spaced multimode waveguides don't crosstalk. Where is the sweet spot for board-level optical interconnect?

DNP brought polymer waveguides on glass down to a 10 µm pitch, but the real point is an iron rule: density is paid for with index contrast. Only Δ=2.3% pushes 10 µm crosstalk down to −32.3 dB. Which three material parameters decide whether polymer waveguides can compete?

Sumitomo Electric expands the beam to 32 µm with collimation mirrors, taming two optical-coupling killers at once: a 3 µm misalignment costs only 0.2 dB, and displacement from 25 to 80°C stays under 0.34 µm. Why is beam expansion the key to flip-chip coupling of PICs onto glass waveguide substrates?

Token demand wants 10x a year while supply delivers only 2x, and the compounding 5x gap can only be closed by architecture. Ayar Labs CEO Mark Wade's key line at OCP APAC wasn't about CPO but this: the unit of adoption shrinks from a whole rack to a single chassis.

Edgecore admitted 1.6T LPO is "not yet successful," so the stopgap is gone and CPO can no longer wait a generation. Three MSAs at OFC 2026 push CPO toward swappable engines, while SONiC only now has the models it needs. Hardware decides who ships; software decides who deploys at scale.

Intel's ECTC 2026 paper swaps the flexible fiber array in a detachable CPO connector for a rigid glass coupler. The point is not lower loss but turning fiber alignment from on-site craft into a process-locked, manufacturable, traceable step.

CPO stalled for ten years not because the technology fell short, but because it wasn't yet a real problem. At OCP 2026 APAC, NVIDIA redefined CPO from "can it be built" to "can it be mass-produced," citing 10x MTBI and Spectrum-6 CPO now shipping in volume.

KYOCERA breaks low-loss coupling for CPO modules into three parts: face-down cooling, a curved mirror and a wide-tolerance core. Coupling loss halved to 1.22 dB, ±5 µm tolerance, error-free from 0 to 70°C. Why can't you judge a coupling module by a single loss number?

Silicon modulators hit an RC bottleneck at 50–60 GHz. Nokia Bell Labs flip-chip integrated a TFLN modulator with a commercial driver IC to build the first CPO transmitter of its kind: Vπ·L 2.3 V·cm, EO bandwidth >45 GHz. Coupling loss and heat are the next hurdles.

The star of GTC Taipei wasn't Vera Rubin, but Jensen Huang's new definition of computing: agentic AI is a computer taken completely apart. Once compute is disaggregated, the optical links that stitch it back together turn from a cost item into the critical path to revenue. The real signal hides in one line: every watt is revenue.

Jensen Huang declared that "compute has been disaggregated"; Matt Murphy supplied the missing physical timeline. AI's next bottleneck is connectivity, and the deciding factor is a copper wall moving into the rack. Every doubling of bandwidth halves copper reach — at 400G/lane, copper can't even span a single rack, and physics forces CPO from slideware into shipments.

Twenty-four sessions at OCP APAC 2026 told the same story: the AI infrastructure bottleneck is shifting from how fast you compute to whether you can connect it and keep it running. Here is the full map, with an index of all 24 session notes.

GlassBridge isn't a connector; it is Corning's second move to extend its glass materials dominance. It targets fiber coupling and FAU, the stage that drives 60-70% of CPO cost. The disruption is real, but the hurdle is commercial, not technical. Why will this hit valuations before fundamentals?

CPO decks spend 90% of their time on chips, but data center operators ask one question: can you swap the fiber? The fiber array unit (FAU) is now a battleground of four coupling physics, with fifteen companies staking out positions.