2026 OCP APAC Summit Full Readout: 24 Sessions, One Story
August 11-12, 2026, Taipei Nangang Exhibition Center, Hall 2. STT covered 24 sessions on site and wrote each one up as its own post. This piece is the full picture that emerges when you stack all 24 together.
The bottom line first: the AI infrastructure race has shifted from "how fast can you compute" to "can you connect it, and can you keep it running."
[Full index] All 24 posts are free to read (in Chinese)
1. Infrastructure and systems
2. Packaging, cost and the route battle
SemiAnalysis | Dan Nishball | Scale Up Sophistry: copper vs. optics is a false choice
Astera Labs | Jeffrey Kung | Optical Scale-Up Fabrics for Next-Generation AI Infrastructure
Linque | Jonathan Förste | Fast Optical Circuit Switching in the Scale-Up
Coherent | Anna Tatarczak | At 400G/lane the bottleneck is electrical, not optical
PCIe 7 makes the retimer mandatory: Astera Labs on where copper runs out beyond 128 GT/s
3. CPO focus: from a technology debate to a yield debate
24 sessions, really just four layers
The agenda looks scattered, but it falls neatly onto four layers.

Scale-up (within a rack to across several racks) is where the firepower is most concentrated. The physics is simple: copper's reach shrinks as data rates rise, about 2 meters at 112G/lane, about 1 meter at 224G/lane, and only about 25 centimeters at 448G PAM4. As the scale-up domain grows from 72 GPUs to 1,024 or more, copper physically cannot connect them all.
Scale-out (across racks within a cluster) is already at the 102.4 Tbps single-chip generation, with 204.8T next and 409.6T after that.
Scale-across (across data centers) comes in three distance tiers of 500 meters, 2 kilometers and 10 kilometers (per NVIDIA), and is still at the proposal and PoC stage.
Power and cooling looks the least glamorous but is the ultimate ceiling for everyone: single racks are heading toward a megawatt, and liquid cooling has gone from an implementation detail to an architectural prerequisite.
And all four layers stand on the foundation of advanced packaging and test.
The four hardest numbers of the event
409.6T. Arista's Andy Bechtolsheim gave the only hard timeline of the event: 102.4T is doable with pluggables, 204.8T is still OK, but 409.6T (roughly 18 months out) gets really hard, because a 409.6T switch needs 204.8T per side, while the CPO optical engines the industry is building today are around 6.4T. The density does not add up. (Note he means optical density for a single 409.6T chip with 204.8T per side; 409.6T systems built from multiple 102.4T chips already exist.)
41% → 28%. SemiAnalysis's Dan Nishball: after HBM is spec'd down, memory's share of system TCO falls from 41% to 28%, freeing up about US$2 million per system, while scale-up connectivity cost per GPU rises from about US$4,000 to about US$11,000.
0.15 dB. SENKO's detachable fiber interface gets repeatability down to 0.15 dB (3σ) and interchangeability down to 0.5 dB (3σ). Repeatability decides whether CPO can be serviced; interchangeability decides whether CPO can be mass-produced.
The fourth is "no number." ASE's Nicole Tien made the most honest remark of the event: almost nobody is talking about yield testing for optical engines (KGOE). The event was full of Tbps and pJ/bit figures, yet not one company disclosed its optical engine test yield.
That "no number" is the most important signal of the event.
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That wraps up the key takeaways of this post.
STT's full analysis is in the paid section: why the CPO narrative shifted across the board this year, how the 409.6T wall will rewrite the pluggable camp's timeline, which layer the budget freed by HBM down-specs actually flows to, what three MSAs launching at once means for Taiwanese suppliers, plus the seven verifiable signals I will track over the next 12 months and a full Taiwan supplier positioning table.
👉 Subscribe to the STT paid section and read the full analysis on vocus (in Chinese):




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