2026 OCP APAC Summit | CPO / NPO / XPO Panel: Not a Route War, but the 409.6T Wall 18 Months Away
A panel is only as valuable as its seating chart. These six seats span optical interconnect from materials and wafers to optical engines and switch systems, and their positions conflict with one another, which is exactly why the consensus they reached is credible.
Gilad Shainer | NVIDIA: currently the only system vendor shipping CPO switches to customers, representing the buyer-plus-system-integrator view
Mark Wade | Ayar Labs: optical engine startup building EIC + PIC and microring WDM, representing the side that wants to put optics right next to the GPU
Subi Kengeri | Applied Materials: the only equipment vendor on stage, looking three to five years ahead at materials and process bottlenecks
Thomas Barber | GlobalFoundries: silicon photonics foundry responsible for optical engine manufacturing and fiber coupling solutions
Andy Bechtolsheim | Arista: switch system vendor speaking for the pluggable / XPO side
Bob Wheeler | LightCounting (moderator): optical communications market research firm; he set the topics and pacing of the session

None of the six speakers defended their own route. The real consensus: where you integrate is not a technology choice; it is a choice about supply-chain bargaining power.
The two Quantum-X design revisions NVIDIA disclosed were all in connectors, fiber entry and liquid-cooling mechanics; not one was optical. The CPO volume-production bottleneck is moving downstream.
Ayar Labs says customers fully buy into CPO's benefits; what holds them back is when their supply-chain risk threshold gets crossed. Renewed interest in NPO is not a technical preference; it is an installment plan.
Arista's Bechtolsheim gave the only hard timeline: 102.4T is doable with pluggables, 204.8T is still OK, but 409.6T will no longer hold in roughly 18 months.
For Taiwanese suppliers: MPO giving way to MMC, 45 µm micro bumps moving to 6 µm hybrid bonding, permanent V-groove attach on its way out, and system-level PDKs built from scratch. All four inflection points fall on packaging, connectors and simulation tools.
1. The Real Fight Is Not Technology, but Who Can Absorb Supply-Chain Risk
Moderator Bob Wheeler (LightCounting) opened by explaining why he organized the session: the photonics industry has suddenly taken broad interest in Near-Package Optics (NPO), while the XPO MSA extends the pluggable roadmap beyond 12.8T. Three routes alive at the same time is itself a signal.
NVIDIA's Gilad Shainer dismantled the "A vs. B" framing with his very first remark:
It's like asking whether a car or an airplane is better. It depends on where you're going. If you just need to get to the next room, an airplane is overkill.
It sounds like diplomatic hedging, but Ayar Labs' Mark Wade brought it down to earth. Their earliest customers were top GPU and accelerator makers who were "very excited" about Co-Packaged Optics (CPO), but Wade pivoted: not every end customer who wants to build an SoC has the same relationship with the supply chain that NVIDIA does.
This is the real theme of the whole session. Nobody disputes CPO's advantages in power, bandwidth density and cost; the dispute is whether you can afford to lock back-end packaging capacity into your own product cycle. Wade described customer decisions in terms of "when the risk threshold is crossed", which is procurement language, not engineering language. So how do his customers view NPO? "I want to take a step toward CPO's benefits, but de-risk the supply-chain path first."
NPO is not a technology route; it is an installment contract. We break this down further in Is NVIDIA's shift from CPO to NPO bad news for the laser supply chain?.
2. NVIDIA's Two Design Revisions Were All Mechanical, Not Optical
Quantum-X is among the first CPO systems shipped to customers. Every lesson Shainer shared from the early ramp was a non-optical issue:
Gen 1 used MPO connectors and quickly switched to MMC: smaller, and easier to plug and unplug within a fixed faceplate size.
Fiber entry moved inward from the outside, reducing hand contact during installation and seating all the way in.
Gen 2 added a door: open it to see the LEDs and operate; close it to prevent accidental contact, all still hot-pluggable.
100% liquid cooling from the design stage.
As for the "real optics" such as microwave modulators and fiber array attach, Shainer said enough upfront research had been done that they were locked in from the start. The market has spent two years asking about CPO yield, but NVIDIA's own iteration list tells you: the bottleneck has moved from optics to connectors and mechanical parts.
Why did Gen 1 use only 1.6T optical engines with unremarkable density? Shainer's answer was the most complete architectural argument of the session: we are not optimizing a component; we are optimizing the entire system. They do not want signals going from a small pipe to a big pipe and back to a small pipe, which hurts efficiency; that is why the whole fabric runs 800G rather than 1.6T. On top of that, topology is moving from multi-tier to multi-plane (tuning both the number of planes and the number of rails to improve resilience and radix), so optical engine size is a dependent variable of topology, not a spec you can optimize in isolation.
He followed with the most business-flavored point: the data center used to be where you spent money; today the AI factory is what makes you money, hence the name factory. When you build something extremely expensive that is supposed to earn money for you, the result is heavy customization; there will be no one-size-fits-all.
3. The XPO Arithmetic and the 409.6T Deadline
In his questions, moderator Wheeler laid out XPO's spec and price band at 12.8T: roughly 16 x 800G ports, with the DR module at about $4,000 in high volume; Bechtolsheim did not dispute that order of magnitude.
Wheeler then pressed on the risk side: one failure takes out 16 ports at once. Bechtolsheim acknowledged the larger unit size, but offered a hedge: based on modeling and field data, the failure rate is the same as today's single module, while density is 8x, which amounts to an order-of-magnitude improvement in reliability.
GlobalFoundries' Thomas Barber backed that premise with Meta data from two years ago: in module failure statistics, the No. 1 cause was "unknown". Swap the module and the system works, yet inspecting the removed module afterward turns up nothing.
Pluggables get blamed for everything because they are the easiest thing to swap. But they take far too much of the blame.
Barber also explained that the optimal XPO solution is not to lay pluggables flat on the board; that is fastest but not smart. The real approach is to merge multiple PICs: today you need eight 1.6T devices; moving to 6.4T, one PIC per board, peripheral electronics consolidate heavily and component count drops significantly. But he drew an honest line: it still cannot reach the three-piece simplicity of CPO with EIC + PIC + direct fiber attach.
The hard timeline Bechtolsheim repeated twice: 102.4T is doable with pluggables, 204.8T is still OK, but at 409.6T, roughly 18 months away, it gets really hard. A 409.6T switch means 204.8T per side, and the current generation of silicon photonics devices simply does not match that.
So his conclusion is not "CPO wins", but this: the CPO people are actually building today is 8, 16 or 32 channels, about 6.4T, a density pluggables can also reach, so it is not compelling enough; what is really interesting is 25.6T-class devices. What is missing is not optics but standards. He explicitly called on OCP to create a mechanical-electrical functional reference interface so multiple parties can design and build ultra-high-density optical engines that mate with different GPUs or switches. His closing line was pure Bechtolsheim: "If you want it out in two years, you have to start now."
A note on the OCI (Optical Compute Interconnect) MSA: the first products launch next year, all using an inverse gearbox, in both OCP and XIO form factors, with added power comparable to LPO-class high-speed solutions. Wade added the capability boundary: they have built microring devices at 50 GHz, 100 GHz and 212 Gb/s PAM4, and 100G NRZ for several years; asked about microrings at 400 Gb/s PAM4, he said, "Some people will say yes, but I start getting nervous." As for why OCI starts at 50G: given the customer SoC's escape bandwidth and the total radix coming out of the package, Gen 1 is enough. How this slow-and-wide path diverges from the fast-and-narrow scale-out path is compared in full in After copper runs out for AI: seven paths for scale-up optical interconnect.
4. The Thermal Problem Is Not the Average, It Is the Cycling
Applied Materials' Subi Kengeri, the only equipment vendor on stage, gave thermal numbers worth noting: the roughly 900 mm² monolithic silicon on NVIDIA's roadmap averages about 4 W/mm², but that is just the average; specific workloads hit 8, 9 or 10 W/mm².
What he really wanted to stress was not the peak: advanced packages contain too many materials with widely different coefficients of thermal expansion (CTE), and thermal cycling and variation driven by workload differences are the real threat to reliability.
From this he made the most concrete industry proposal of the session: PDKs have so far been device-centric; what is needed now is a system-level PDK that can simulate electrical, optical, thermal and multiphysics domains, machine readable, with standardized templates (process details may differ by fab, but the template must be consistent). His reason in one line: you cannot design what you cannot simulate. We explained what this means for the silicon photonics barrier to entry in Why is silicon photonics so hard to design? The answer lies in a box called the PDK; now Applied Materials wants to scale that box from devices to systems.
He also gave a hybrid bonding update: pitch is approaching 6 µm and will go lower, with I/O energy efficiency expected to reach about 1 pJ or even sub-1 pJ. Compare that with the Gen 1 optical engine micro bump pitch Barber cited, 45 µm; the gap in between is the road packaging houses will travel over the next three years. As for the root cause of lower power, Barber was clear: move electro-optical conversion as close as possible to the XPU or switch, turning today's three retimed electrical segments into a single end-to-end link with no retimer, provided the EOE loss fits within a single link budget.
5. Materials and Coupling: Silicon Modulators Push Back on TFLN, V-Groove Is Out
Asked which modulator material wins as 200G/lane moves to 400G/lane, Barber offered a counterintuitive observation: at OFC two years ago, 400G modulators were 100% TFLN; at this year's OFC, you saw a lot of silicon modulators. His view is that IM/DD (intensity modulation used for DR and FR) can be pushed all the way with pure silicon; it is coherent that really needs new materials. When bandwidth goes from about 110 GHz to about 130 GHz, silicon may be pushed too far, and that is when TFLN, BTO or polymers are needed.
Wade added a designer's perspective: it is not a linear decision of "I'm at 100G, so next is 200G, then 400G". The OCI MSA actually goes back to slower and wider, and the 400G devices they have seen tend to be large; when the goal is to raise bandwidth density and radix together, going to 400G is not necessarily worth it.
On the coupling side, Barber said something with major implications for the FAU supply chain. GF used to push V-groove edge coupling and now talks about surface coupling, because:
V-groove is a permanent attach. You can't use permanent attach for CPO: you have to put the optical engine into the XPU, onto the PCB, into the server, and those fibers will break. Trust me.
Fiber has to be attached at the very last moment, so V-groove is out. Interestingly, Corning's glass bridge actually leverages GF's V-groove: the glass bridge overhangs the die edge and light enters horizontally, without the dual-mirror turn of TSMC COUPE or GF's own solution; the trade-off is a large structure overhanging the die edge that needs separate mechanical stabilization. It is a trade-off between mechanical stability and optical alignment, with no outright winner. We discussed the material-dominance implications of Corning's move in Corning GlassBridge: glass material dominance extends from package substrates to the fiber coupling layer. Wade added just one line, but a weighty one: he hopes the physical optical interface will converge across foundries; otherwise back-end equipment and component makers will have to handle a pile of incompatible interfaces, and the toolchain cannot be sustained.
Two short answers worth noting. Security: Bechtolsheim was blunt. Optical modules are passive forwarding devices that initiate nothing; security lives at the system level; the control plane is low-speed with zero connection to the high-speed data path. "Saying you can intercept traffic inside the module and send it somewhere else is nonsense." VCSEL: the industry has made significant investment in 50 GHz-class slower-and-wider VCSELs, and he previewed that Lumentum and Coherent will present related work at the OCP Summit in October.
6. What It Means for Taiwan's Supply Chain
The panel never mentioned Taiwan once, yet all four inflection points land squarely on Taiwanese suppliers' positions.
Connector specs are changing generations. MPO being replaced by MMC is not a catalog refresh; density and pluggability are being redefined. At the layer of SENKO, FOCI, Largan and Amphenol, whoever can fit more fiber cores into the CPO faceplate space budget while keeping low loss and pluggability earns a ticket in. We broke down how hard this step is in Fiber-to-chip: the least sexy step in CPO, and the one blocking everyone.
45 µm micro bumps to 6 µm hybrid bonding is a clear path. ASE, Amkor and TSMC are all running it, but two speakers both stressed reliability risk from thermal cycling: whoever can provide thermal-cycling lifetime data is the one truly ready.
Permanent V-groove attach on its way out is a watershed for FAU makers. Detachable interfaces, surface coupling and glass bridge solutions will split the market; vendors betting on permanent-attach production lines need to replan.
System-level PDK is a complete blank for Taiwan. The say currently sits with foundries and equipment vendors, but what can turn it into usable tools is the design services and EDA ecosystem, one of the few high-value links where Taiwan has not yet staked a position.
As for XPO economics: 12.8T at about $4,000 for 16 x 800G ports works out to about $250 per port. For module makers this is not doomsday but a lifeline; yet Barber was blunt that component count will drop significantly. It extends the life of module makers while cutting volume for passive component and parts suppliers.
Conclusion
The most valuable thing about this panel is that six people with completely different positions made no attempt to declare a winner: customization will replace standardization, customers are waiting for a risk threshold, pluggables take unfair blame, simulation tools come first, and today's CPO density is not compelling enough.
Stack them together and the answer emerges: CPO vs. NPO vs. XPO is a false debate. They are three SKUs on the same optical engine production line, differing only in how far from the XPU you place the electro-optical conversion, and that distance is set by your supply-chain bargaining power.
The only non-negotiable is Bechtolsheim's line. In about 18 months, switches will need to push 204.8T per side, and current silicon photonics device density cannot keep up. To deliver 25.6T-class optical engines by then, design, reference interfaces and back-end test capacity all have to start today.
So what to track next is not who is hyping CPO, but three signals: whether OCP actually starts that high-density mechanical-electrical reference interface; when hybrid bonding thermal-cycling lifetime data goes public; and the first slow-and-wide VCSEL specs at the October OCP Summit. If any one of these lands, the balance will tip to one side.
This article is for technology and industry trend analysis only and does not constitute investment advice.
Related Reading
CPO is no longer "crying wolf": six real signals from the LightCounting CPO/NPO conference: the annual conference of the moderator's firm, with first-hand signals of renewed NPO interest.
[CPO Breakdown 1/6] Have pluggable optics hit the wall? Understand this wall before you understand CPO: to see where the 409.6T deadline comes from, start with this power wall.
Technical Article Analysis | When XPU heat sits directly on the photonic chip: imec quantifies the thermal cost of 2.5D/3D CPO in 18 figures: the thermal-cycling risk Kengeri described, fully quantified in an imec study.




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