ECOC 2026 | No Single Winner After 1.6T: Six Panelists Move the Scorecard from pJ/bit to FIT
1. Why this panel deserves a word-by-word read
At 4 p.m. on September 22, 2026, the final Market Focus panel at ECOC 2026 — “Realistic check of AI interconnect scaling solutions for post 1.6T era” — was moderated by Frank Chang of Source Photonics. Six people sat on stage: Scott Wilkinson of Cignal AI (analyst), Andy Bechtolsheim of Arista (systems), Mark Filer of Oracle OCI (end user), Craig Thompson of NVIDIA (platform definer), Sanjai Parthasarathi of Coherent (component supply), and Ryan Yu of TeraHop (optical engines and MSAs).
This lineup laid out the entire AI interconnect chain in one go, from “who pays” to “who makes the parts” — and nobody talked about visions. They talked about numbers already shipped, LTAs already signed, and quarters already locked in. There have been far too many CPO sessions this year, most of them stuck on which architecture wins. Nobody argued architecture here. What they argued about was how many pJ/bit each reach should cost, and what evidence a new technology must bring to prove it won't knock an AI factory offline in the middle of the night.
2. Andy Bechtolsheim: the topic is density, not port speed
Arista co-founder Andy Bechtolsheim upended the premise with his very first slide: “The Topic is Density, not Port Size”. Today's largest Ethernet port is 1600G, and 3.2T Ethernet “won't arrive for several years.” So what is actually scaling in the meantime? He listed three things: SerDes speed (200G→400G), channels per PIC (8→16→32→64), and module packaging density (8→16→64). Push all three axes together and the result is higher density and lower cost and power per bit — not a bigger number in the port-speed column.
That set the tone for the whole panel. For the past decade, the optical communications narrative was “how many T is the next generation.” From 2026 on, it becomes “how much bandwidth fits in the same square meter of data hall, and how often that bandwidth breaks.”
His second slide, “The Major Fork In the Road,” was even more important: so far, scaling has come from faster SerDes (100G→200G, with 400G around the corner), and the beauty of high-speed SerDes is that it supports the entire physical-layer spectrum — copper, RF dielectric waveguides, IM/DD all the way to coherent — and can even support slow-and-wide VCSELs and OCI through a reverse gearbox (e.g., 200G-PAM4 ↔ 4×50G-NRZ). The conclusion in one line: high-speed SerDes remains the mainstream path to faster I/O.
In other words, every scheme that claims to bypass SerDes eventually has to plug back into SerDes — and the adapter that does the plugging turns out to be the most expensive line item of the whole panel.
3. Five reaches, five different winners
Bechtolsheim split AI interconnect into five reaches, each with different requirements:
Scale-up (in-rack): 2 m
Scale-out (in the data center): 500 m–2 km
Scale-across (campus): 2–20 km
Scale-across (metro): 100 km+
Then came a very Arista line: every use case wants the same thing — lowest power, lowest cost, lowest failure rate. The only difference is that the technology that delivers those three at each reach is not the same one.
On the in-rack reach he was categorical: copper cables and copper traces are the undisputed king of rack-level interconnect — lowest cost, lowest power, lowest failure rate — and that is “unlikely to change for the foreseeable future.” NVIDIA would repeat the same point later in almost the same tone.
The real fight is at 10 meters. He listed five technologies competing on cost, power and reliability: dielectric waveguides, RF microwave, slow-and-wide VCSEL arrays, slow-and-wide DWDM, and “fast & narrow” optics built with advanced packaging. Four slides gave the specs:
Dielectric RF/microwave: reaches 100 GHz and supports 400G-PAM4 over 10 m; no lasers, no photodetectors, no precision optical alignment, and cost lands in the active copper cable (AEC) price band.
Slow-and-wide VCSEL: an 8:1 reverse gearbox (4 pJ/bit) plus 8×50G-NRZ VCSELs (1 pJ/bit), splitting eight 400G-PAM4 lanes into NRZ channels, with room for spare channels to buy reliability.
Slow-and-wide DWDM: a 4:1 reverse gearbox (4 pJ/bit) plus 4×100G-NRZ BiDi DWDM — the two forms of OCI (8×50G-NRZ or 4×100G-NRZ), running 800G over a single bidirectional fiber.
Fast-and-narrow BiDi: 400G-PAM4 DR8 plus BiDi with an LRO retimer in front, 800G per fiber, halving the fiber count — and the very same optics can be reused unchanged for scale-out.
Finally he plotted these technologies on a logarithmic reach axis: active copper at about 4 m, dielectric at about 10 m, VCSEL at about 30 m, and OCI and DR8 stretching past 500 m. The best choice depends on the reach requirement — that is the reach map mentioned at the start.
Flatten out his later 12.8T XPO technology comparison table and the map gets a price list:
This table is worth pausing on: from 4 m of copper (4 pJ/bit) to 100 km of ZR (24 pJ/bit), reach spans four orders of magnitude while energy rises only sixfold — the result of three decades of optical communications grinding out a dedicated solution for every reach. The new problem for AI data centers is that they need all five reaches at once.
4. XPO: dunk the pluggable in liquid cooling and trade density for half a data hall
What Bechtolsheim was really selling was XPO — a 12.8T liquid-cooled pluggable module. One XPO replaces eight OSFPs, with roughly 4× the front-panel density. Two 32-lane paddle cards sit back to back around a shared cold plate, with two high-speed edge connectors plus a separate power connector, and it is compatible with existing 8-lane silicon photonics engines.
He made the case with data-hall arithmetic: 512 GPUs doing 25.6T scale-up need eight switch racks with OSFP — more switch racks than GPU racks. With XPO, only two racks are needed, cutting floor space in half.
The reliability argument was just as direct: far fewer components than eight OSFPs, lower component temperatures, smaller temperature swings (less thermal stress), clean linear electrical channels, and a more reliable switch main board — the conclusion being a failure rate far below that of eight OSFPs. This is fully in tune with what Oracle and NVIDIA said later: the selling point of this generation is not lower power but fewer failures.
Technically, he left no gaps either. Simulation of the XPO edge connector at 448G: estimating 448 Gb/s per electrical lane, 448G PAM4 needs about 112 GHz while PAM6 lands at 87–90 GHz — numbers that echo the main theme of another workshop at this ECOC, which we broke down in full in ECOC 2026 | Fast-and-narrow vs. slow-and-wide argued for three hours, and nobody defined “slow” first.
XPO also reaches further than you might expect. He showed a 12.8T Coherent-Lite XPO developed with Ciena: the Kari 3.2T Coherent-Lite ASIC (2nm CMOS, 2×1600CL per chip, OIF 1600CL at 235 GBd, 16×200G SerDes), dual 1.6T ICR/TIA, dual 1.6T MZM/driver, and dual O-band DFB lasers; one paddle card carries 6.4T and two make 12.8T — 8×1600CL on the optical side and 64×200G on the electrical side. Add a version with an integrated 8-channel MUX and a single module needs just one TX/RX fiber pair on an LC connector, matching CPO-architecture front-panel density outright. Even more aggressive is a line-system version that integrates the EDFA and MUX/DEMUX: 800G coherent ZR span extended from 80 km to 180 km, saturated output >23 dBm, power <30 W, and 16× smaller volume. The next step is 25.6T (400G/lane), with 16 modules per 1OU and 512 per rack, which equals 12.8 Pbps per rack.
For why the Coherent-Lite line matters, read it alongside ZR is the meat, Coherent Lite is the bone: as scale-across moves down from telecom-grade ZR to data-center-grade CL, optical module makers' product portfolios will be redrawn.
[Insert image here: IMG_2639 — XPO coherent roadmap: 12.8T→25.6T per module, fixed-wavelength lasers to cut cost, liquid cooling to raise reliability, 12.8 Pbps per rack | A. Bechtolsheim (Arista), ECOC 2026]
5. Oracle's counterpoint: CPO is great, but your failures come from those 4,096 contacts
Mark Filer spoke for end users and framed everything around TCO from the start: reliability and availability (network uptime, higher MFU, avoiding service credits), power efficiency (every watt saved in the network is compute you can sell), and capex — where he flagged a specific trend: network spend is rising every year relative to compute spend, and that trajectory is unsustainable.
Oracle's decision for 1.6T is clear: LRO/FRO pluggables are already the plan of record, with deployments this year. What about post-1.6T? He is also looking at CPO, and believes CPO improves TCO on three axes: reliability (optical module mishandling is one of the main failure modes in data centers; CPO hides it behind the wall and takes people out of the deployment process), power (versus fully retimed pluggable systems in the 200G/lane generation, up to 50% savings, per NVIDIA data), and cost (30%+ in theory, possibly more at volume).
But on the next slide he turned the knife: today's CPO is a proprietary, vertically integrated implementation that brings supply chain constraints; and with nothing but DR optics around the ASIC, it isn't flexible enough — what if I need FR or ZR?
That is where NPO fits. He listed three kinds of flexibility: a multi-vendor optics ecosystem (no end user dislikes competition); a much lighter RMA process, where ODMs/OEMs can rework in place instead of swapping the whole box; and the ability to late-bind the optical PMD, mixing DR/FR or even running a few ports to the front panel via flyover cables to plug in ZR. The Open CPX MSA is one such implementation. But he added a caveat: NPO must prove reliability and power on par with soldered-down CPO.
Then came the most damaging part of the panel. Everyone talks about lasers when they talk about CPO, he said, but hardly anyone talks about connectors. Take a 409.6 Tbps CPO switch: 512 ports of 800G DR4, 512 × 8 fibers = 4,096 physically contacting fibers crammed onto the front panel. And the failure distribution Oracle compiled from its own deployments is:
In AI back-end networks, more than 90% of link failures are contamination-related (dust, debris, oil, scratches — worse in regions with clay-rich soil)
Of the optical modules sent to the analysis station, 97% were diagnosed as contaminated, dirty or scratched
What does that mean? On that 4,096-fiber box, a single fiber not cleaned properly means the whole unit goes back to the vendor.
His answer is expanded beam optics: the beam is expanded before the mating interface, making it insensitive to dust, debris and oil; the ferrule is recessed to avoid direct contact with contaminants; and some designs (such as 3M's) use a 90-degree turn to keep the optical path inside the housing. The upside: no contact means no need for compression, cutting mating force by about 20×, with greater tolerance for insertion loss and reflection. Oracle co-chairs the EBO MSA.
Low mating force opens another door: ganged connectors and blind-mate backplanes. He showed a Broadcom/Molex rack concept — liquid-cooling supply and return, power bus bars, fiber shuffles, an optical flexplane, CPO switches and blind-mate connectors all moved to the back of the rack, leaving no fiber on the front panel at all. If a switch fails, you pull it out and push a new one in, powered up and back in service within five minutes, without touching a single cable.
This thread ties directly into the connector standards battle; read it together with Breaking down Open CPX 1.0: CPO finally gets a standard socket.
6. NVIDIA: copper stays, OSFP stays, and CPO is sold on “it doesn't break”
Craig Thompson opened with self-deprecation: “There's someone at our company who loves to talk about roadmaps and announce products. That person isn't me.” Then every sentence he said drew a red line.
First, scale. Vera Rubin NVL72: 3.6 EFLOPS of NVFP4 inference (5× Blackwell), 2.5 EFLOPS training (3.5×), 75 TB of fast memory (2.5×), 1.6 PB/s of HBM4 bandwidth (2.8×), 260 TB/s of scale-up bandwidth (2×), 115 Tb/s of scale-out bandwidth (2×), and 130 TFLOPS of in-network compute (2×); overall 10× energy efficiency, 1/10 the cost per token, and 1/4 the GPUs to train the same model.
Then came the line that will make many people uncomfortable: everything inside the rack is copper. Copper backplanes are reliable, cheap and low-power; “it makes no sense to give up copper backplanes until we are forced to,” and “I won't predict when that will be, but it won't be soon.” How does NVL576 work? By connecting eight 72-GPU racks — with half of the NVSwitch bandwidth going optical and the rest staying on copper.
Third, he spelled out the relative scale of scale-up and scale-out: scale-up bandwidth is roughly 10× scale-out (1.6T of scale-out per GPU and 115 Tb/s per rack, versus 260 TB/s of scale-up). His logic: you cannot introduce a pile of new technologies and new risks on the network carrying 10× the bandwidth all at once, so technology proven in scale-out should be carried over to scale-up as much as possible.
Fourth, OSFP remains the workhorse. Cumulative OSFP shipments are in the tens of millions; 1.6T modules have been shipping for more than a year, in the millions, used in both Vera Rubin compute trays and Spectrum-6 switches; 200G/lane still has several generations to run; logically the next step is 400G/lane, “but we haven't chosen it yet.” His requirements for optical modules sound boring but are fatal if missed: near-zero pre-FEC errors, consistent FEC bins, and error-free operation even under bursty traffic — “at this cluster size, link reliability is everything,” and he will never trade reliability for power efficiency.
So why bet so heavily on CPO? His answer had nothing to do with power: “We are investing in CPO for long-term integration, because integration brings a more reliable network.” The goal is to drastically cut disruptive events — those link flaps and signal-integrity issues. The system is tested known-good in a clean room, packaged, and rolled into the data center without anyone touching it before it is plugged in. The Spectrum-X Ethernet Photonics numbers: micro-ring modulator CPO chips in volume production, 3D-stacked silicon photonics engines on TSMC's COUPE process, high-power high-efficiency lasers, and detachable fiber connectors, resulting in 1/4 the discrete components, 5× lower power and 10× MTBF.
When the moderator pressed on market share, he answered with one sentence: “If we are successful, CPO will become the primary optical interface on our switches.” As for optical interposers, he was calm: that is a huge packaging problem, and moving on it requires a big enough reason — bandwidth density or a drastic cut in PHY power — “we won't rush into it.”
7. Coherent and TeraHop: quarters and FIT on the table
Coherent's Sanjai Parthasarathi opened with market numbers: a 2030 SAM of more than US$60B for the existing portfolio, plus more than US$30B for CPO/NPO/chip-to-chip (citing Dell'Oro, LightCounting, Cignal AI and internal estimates).
Then came timelines, stated very firmly:
CPO with ELS (silicon photonics with InP ultra-high-power external lasers): more than 10 active customer programs, anchor customers and long-term agreements (LTAs) already signed; volume production timing is scale-out in Q4 2026 and scale-up in 2H 2027.
NPO modules: a 6.4 Tb/s silicon photonics NPO (32×200G) and a 2D VCSEL array NPO were both shown at OFC 2026; Coherent is a founding member of Open CPX.
2D VCSEL arrays: 25 Gb/s to 200 Gb/s per emitter, production-ready in 1H CY27; a high-density version packs 37 channels into a tiny package and collects all 37 lanes with one multicore fiber, production-ready in 2H CY27, measured at 1.2 pJ/bit and 12 Gb/s/mm² (including laser, driver, PD and TIA).
Chip-to-chip: more than 5 customer programs, timeline 2029–2030, in the form of an optical interposer between xPU and HBM, with external lasers plus DWDM multiplexing and circulators.
TeraHop's Ryan Yu laid out Open CPX progress: Rev 1.0 was released on September 16, 2026 and made public the next day. Membership has passed 46 companies, with Ciena, Coherent, Marvell, Molex, Samtec and TeraHop as founding members. The spec defines four NPO/CPO module form factors and two connector classes (Type 1 separates RF from DC/low-speed, Type 2 integrates them in a single connector). Applications cover NPO for xPU scale-up, NPO/CPO for switches, and IOA (optical engines built on HDI boards and attached next to the ASIC substrate through elastomer high-density connectors) — Broadcom's Tomahawk 6 has announced support for this form.
His roadmap lines up the whole chain: 1.6T OSFP is in full volume production; IMDD moves from 1.6T to 3.2T in 2027–2028; the 12.8T XPO MSA and 6.4T Open CPX are both expected to reach volume deployment in 2027 (with 25.6T XPO+ already in early development); while “slower and wider” (SAW) scale-up is still at the PoC and demo stage, with a question mark over its volume production date.
On the hardware side, TeraHop's 6.4T Open CPX optical engine “Diablo-1” puts the laser inside the engine: typical power <35 W, or <5.5 pJ/b, with a dedicated liquid-cooled cold plate keeping every component (especially the laser) cool. The front panel is clean, with only single-mode fiber coming out — no ELSFPs taking up panel space, no extra polarization-maintaining fiber, no pile of connectors to mate. ASIC-to-NPO insertion loss measured about 12 dB. Arista has also used this engine for a 100 Tbps switch concept design.
8. The panel's hardest consensus: the 4 pJ/bit reverse gearbox tax
Lay Bechtolsheim's slides on top of Ryan Yu's and you see the panel's real verdict.
Bechtolsheim's slow-and-wide power breaks down like this: reverse gearbox 4 pJ/bit + VCSEL 1 pJ/bit; the DWDM version is the same, with the gearbox cell still at 4 pJ/bit.
Ryan Yu's last slide did the same math from a system view. His words were blunt: today you cannot get rid of SerDes, because SerDes still has to support copper and optics side by side; as long as SerDes is there, the new slower-and-wider optics need a reverse gearbox, and that adds about 4 pJ/b. So if you use micro-LEDs or micro-VCSELs but have to pair them with a reverse gearbox, the “ultra-low-power” advantage does not exist right now.
Two companies, two decks, one number. This is the only quantitative conclusion on the panel that was cross-validated — and the line most worth copying into your notes.
For Taiwanese readers, the implication is concrete: until 400G/lane SerDes arrives, none of the slow-and-wide light sources pitched on “ultra-low pJ/bit” (uVCSEL, uLED, OCI) has a real system-level power advantage. Whoever eliminates the gearbox cell first — either through SerDes generation progress or through switch chips natively supporting multi-lane NRZ — is the one that actually earns a ticket in. For the technical background on this thread, see After copper runs out for AI: seven paths for scale-up optical interconnect.
9. Reliability becomes the entry fee: the LPO verdict and the FIT arms race
The first Q&A question went straight to LPO: what share of ports will LPO take over the next two years?
NVIDIA's answer: everything shipping today is fully retimed; Spectrum-6 begins introducing half-retimed; and what ships over the next year or two will be either half or fully retimed. LPO is a non-retimed interface, and NVIDIA believes non-retimed belongs in highly integrated chip-scale packaging — that is, CPO; CPO is a fully linear, non-retimed architecture by design.
Oracle's answer carried more weight because it came with numbers: Oracle has disclosed more than 400,000 800G LPO links in operation, and the 800G generation will remain a mix of FRO and LPO; but at 1.6T, Oracle has decided to stay with LRO/FRO, because “at this scale, the margin with LPO is too close to the limit we can accept.”
Cignal AI's Scott Wilkinson added the analyst's view: their reports have never been able to include LPO volumes because nobody is really using it — “Mark's numbers are the first meaningful LPO data we've seen.” All along, people have said so-and-so is doing it; two weeks ago it was Alibaba, and that didn't pan out either.
This exchange pushed the panel's theme to its final layer: in AI interconnect, the entry fee for a technology is field data.
TeraHop simply demonstrated how to pay that fee: cumulative shipments of more than 25 million silicon photonics optical modules, with cumulative PIC field hours above 100 billion hours and FIT < 0.01; 1.6T silicon photonics OSFPs in volume deployment measured at FIT < 1; extrapolating to a 6.4T NPO (roughly four 1.6T OSFPs) gives FIT < 10; it even gave measured values for CW lasers from two suppliers (FIT 0.01–0.03). The message is clear: no lab can test 100 billion hours, and unless a new technology gets deployed and gets paid first, it is hard to convince a hyperscaler to solder it next to its own substrate.
10. Timeline and risks: what might not hold
Line up the quarters the six speakers named, and the post-1.6T calendar is already quite concrete:
But four points deserve caution:
First, XPO and Open CPX both say “volume deployment in 2027,” yet neither has named a volume customer. MSA membership (XPO bills itself as the largest optical MSA ever; Open CPX has 46+ members) is an ecosystem signal, not a shipment signal — and the two have diverged many times in optical communications history.
Second, NPO reliability has not been proven. Oracle itself was clear: NPO must prove reliability and power on par with soldered-down CPO, and those systems are only now in development — “check back in six months and see where we are.”
Third, the power advantage of slow-and-wide is illusory in the near term. That 4 pJ/b won't disappear on its own; its timing is tied to 400G/lane SerDes and switch-chip support — and NVIDIA said outright that 400G/lane is “not yet chosen.”
Fourth, scale-across is far smaller than scale-up. Scott Wilkinson's order of magnitude: scale-across is currently mostly 800G and heading to 1.6T, and even if it goes very well it is in the two million units range; scale-up is already at the forty million units level and growing fast. These are two markets of completely different weight and should not be served with the same capacity and R&D resources.
11. Conclusion
The single most important takeaway from this panel: post-1.6T is not an architecture war; it is a map that puts a price on reach, power and failure rate at the same time.
The six speakers effectively reached three points of consensus. First, there is no single winner: 2 m goes to copper, 10 m to dielectric, 20–30 m to slow-and-wide optics, 500 m to DR8, and 10 km+ to Coherent-Lite and ZR — whoever tries to take it all gets knocked out first. Second, low-power optics does not mean a low-power system: the 4 pJ/bit of the reverse gearbox is currently the hardest bottleneck for the slow-and-wide path, confirmed independently by slides from two companies. Third, reliability has turned from a marketing word into an entry fee: Oracle used 90%/97% to bring the focus back to connectors, NVIDIA used 10× MTBF to explain why it does CPO, and TeraHop used 100 billion hours to prove it deserves to be soldered next to the substrate.
So if you can track only one indicator, STT's suggestion is not CPO penetration but two milestones: when 400G/lane SerDes is finalized (which decides when the slow-and-wide gearbox tax disappears), and when the first CPO rack with an expanded-beam blind-mate backplane actually enters a data center (which decides when the connector supply chain gets reshuffled). The former decides who gets to play; the latter decides who makes money.
This article is for technology and industry trend analysis only and does not constitute investment advice.
Related reading
ECOC 2026 | Data centers need billions of lasers, yet the bottleneck is the five minutes it takes to “connect” them: a full breakdown of the light-source workshop at the same ECOC, complementing this article's connector argument.
What is XPO? The loudest new scale-up standard at OFC 2026, explained: the fastest place to start for XPO spec background.
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