ECOC 2026 | Three Hours on Fast-Narrow vs. Slow-Wide, and Nobody Defined "Slow": The Real Dividing Line Is 448G
ECOC 2026 devoted its entire opening-day afternoon — two back-to-back sessions, fourteen talks — to one question: can per-lane speed keep climbing, or will "slow and wide" win in the end? The conclusion was that there was no conclusion. But it delivered three things more useful than a verdict.
First, the real breakpoint isn't fast vs. slow — it's the step from 200G to 400G per lane. At a 448G electrical interface, package escape eats 30–50% of the total budget and reach on the PCB shrinks to 10–20 cm. At that point, whether optics moves into the package is no longer a choice; the two camps only disagree on how soon that moment arrives.
Second, nobody in the room defined "slow" up front. The same OCI spec got four different answers under six speakers' six definitions. When everyone's Tbps/mm and pJ/bit figures sit on different lane-rate boundaries, cross-comparisons are invalid until the definitions are aligned.
Third, pJ/bit was quoted anywhere from 0.369 to 20, and most of that 54x gap is not technology but measurement boundary. Coherent laid it out on stage: the sub-1 pJ/bit figures were measured either at the "optical engine" or inside a modeling boundary. Add back roughly 2.0 pJ/bit of SerDes, MCC and clocking, and 0.90 and 1.00 become 2.9 and 3.0 — the same class as the 3.5 that originally looked worst.
For Taiwan's supply chain, the signal comes at the end: after all the arguing, what's holding both sides back isn't the optics — it's packaging, fiber coupling, test, and external light sources.
1. A Whole Afternoon for One Question
In Málaga, ECOC 2026 ran the 90-minute Su3-I and Su4-I sessions back to back, separated only by a coffee break, under one question: Can fast narrow channels keep rising without limit or will slow and wide become the winner?
The chairs were Eric Bernier, Ciena VP of System Architecture Peter Winzer, Tony Chan Carusone, and Marianna Pantouvaki. The first half featured seven speakers from LightCounting, Arista, Qualcomm, Ciena, Huawei, Marvell and Applied Materials; the second half seven from OpenAI, Lumentum, Coherent, HyperLight, Lightmatter, Credo and Xscape Photonics. Buyers, switch vendors, module makers, materials suppliers, startups and analysts were all in one room — rare for an ECOC workshop.
The chair opened by urging the audience to "use every creative question you can to force the speakers to pick a side and say things that might get them in trouble," stressing there was no official recording. Before the final speaker of the second half, he noted the votes had piled up on "coexistence" and reopened the poll — clearly finding that answer too safe. Tally the fourteen conclusion slides, though, and his complaint turns out to be only half right.
Only Chris Cole of Applied Materials and Bilal Riaz of Ciena clearly backed fast-narrow; only Darius Bunandar of Lightmatter and Mohsen Asad of Credo clearly backed slow-wide. The ten in the middle weren't fence-sitting — each spelled out the threshold the other camp must clear to be right. The workshop's value isn't in the vote count; it's in those ten thresholds.
2. A Twenty-Year Axis, and Six MSAs as a Hedge
LightCounting consultant Roy Rubenstein calibrated the scale with one comparison: the Finisar SFP+ at ECOC 2006 was 1G–10G, single-lane, air-cooled; the XPO module at ECOC 2026 is 1.6T–12.8T, 64 lanes of 200G, liquid-cooled. In twenty years, lane count went from 1 to 64.
He then set the two tracks side by side. On IMDD, 1.6T OSFP is in volume, 3.2T is in development (16×200G or 8×400G), and 12.8T is still on paper. On coherent, from today's 200 GBd to 240–270 GBd for 1600ZR (2027/28), 280 GBd for 2.4T (2028), 400 GBd for 3.2T (2029), and 450–500 GBd in the early 2030s.
His read was blunt: AI iterates in months, electrical and optical speeds double in years — something has to give in between. The industry's way of giving is to stockpile options through MSAs — six running simultaneously in 2026: XPO (extending pluggables to 12.8T), CPX (pushing a serviceable interface next to the ASIC), 400G Optics (continuing to push per-lane speed, 500 m), OCI (converting high-speed electrical I/O into more, slower optical lanes, e.g. 200G split into 4×50G), SDM4 MCF (multi-core fiber), and Expanded Beam Optics (expanded-beam connectors to solve volume alignment).
His three-layer chart was the most precise line of the day:
Architecture is a bet. Going wider is not.
Whether per-lane speed keeps rising is a gamble; but "lane count and fiber count will definitely go up" — both sides agree. That was the only consensus in the room, and the starting point for every supply-chain read that follows. For the physical spec of the Open CPX layer, see our full teardown Open CPX 1.0 Teardown: CPO Finally Gets a Standard Socket.
3. The Real Breakpoint: The 448G Step
Arista's Sunil Priyadarshi pulled the question back to "can the switch get its electrical signals out." His bandwidth path: 51.2T (512×100G) → 102.4T (512×200G) → 204.8T (1,024×200G) → 409.6T (1,024×400G). Note the 204.8T generation: lane count doubles, speed stays put; speed only moves at 409.6T. Each way of doubling has its own pain — one is bound by package and bump density, the other by the electrical channel.
At a 448G electrical interface, the numbers turn harsh: PAM4 needs 224 GBd and ~112 GHz of analog bandwidth; PAM6 cuts that to ~173 GBd and ~90 GHz; PAM8 to ~149 GBd and ~75 GHz — but the bandwidth saved is paid for in SNR and DSP complexity. The channel itself is worse: ultra-low-loss PCB runs about 2.1 dB/inch at 112 GHz versus 0.3–0.5 dB/inch for twin-ax, a 4–7x difference.
Letizia Giuliano of Qualcomm Dragonfly supplied the other half of the math: in the 224G generation, BGA/package/PCB escape loss already consumes 30–50% of a 40 dB link budget; at 448G it becomes effectively infeasible. That's why Qualcomm is working with Samtec on "co-packaged copper" — even the copper has to move into the package.
Lightmatter's Darius Bunandar recast the same point as a three-column table: energy goes from ~1–2 pJ/bit for 56G NRZ to ~4–6 pJ/bit for 112G PAM4; electrical reach on PCB shrinks from 1 m to 30–50 cm at 112G and then to 10–20 cm at 224G PAM4; the 448G column simply reads "flyover or CPO only." FEC goes from unnecessary to RS/KP4, KP4+, heavier FEC and higher latency.
Credo's Mohsen Asad closed off the "wait for the process node to save us" route: a 106G DSP SerDes is 3.4 pJ/bit at 4nm — and still 3.4 pJ/bit at 3nm.
Stack the four companies' numbers and the conclusion is clear: the disagreement isn't over whether fast-narrow can continue, but how soon 448G arrives and whether packaging is ready when it does. We covered the context of this electrical bottleneck in At 400G/lane, the Bottleneck Isn't Optical — It's Electrical; ECOC simply filled in the numbers.
4. Three Hours of Arguing, and Nobody Defined "Slow"
This was the most absurd — and most valuable — finding of the day.
Less than ten minutes after Roy Rubenstein finished, a hand went up: "OCI isn't slow at all. I'd call it 'not-too-slow and not-too-wide.'" Roy conceded on the spot that splitting 200G into four 53 Gbaud lanes is less a slowdown than a "translation" — "It's hard to define what truly counts as slow."
Over the next thirteen talks, everyone spoke from their own definition. Ciena's Bilal Riaz simply drew the line at "if it's NRZ, it's slow." Chris Cole used a relative definition: "below a quarter of the highest rate of the day." OpenAI's Binbin Guan was the only one to give an absolute threshold — below 50 Gb/s counts as slow; by that line, OCI's 53.125 Gbaud falls just outside, so OpenAI added a third box, Fast & Wide. Marvell's Lenin Patra inserted a new term in the middle, calling 50G–100G NRZ "Flat Optics" and reserving true Slow & Wide for 2G/4G–50G micro-emitters. Lightmatter's Darius Bunandar moved the definition from speed to packaging: with 3D stacking, the electrical hop is down to microns, 56G NRZ at about 2 pJ/bit is enough, and fast vs. slow loses meaning.
For fairness, here is OCI's actual spec: four 53.125 Gbaud NRZ wavelengths per direction, split into A/B bands, single-fiber bidirectional, 212.5 Gb/s raw, a nominal 200G interface. 53.125 Gbaud is faster than what many people call "fast."
The debate's first concrete output is a negative one: until definitions are aligned, any cross-vendor Tbps/mm or pJ/bit comparison is invalid. That's not rhetoric — the next section shows how big an error it causes.
5. pJ/bit from 0.369 to 20: Most of the 54x Gap Is Measurement Boundary
Coherent's Chris Kocot did what nobody else did: he didn't compare technologies — he compared "where each number was measured."
He put six widely cited energy figures in one table, forcing each row to state its measurement boundary, evidence level and what was left out. The 0.369 pJ/b comb-driven SiPh figure is model-calibrated and excludes clocking (add 0.3–0.6 back); 0.75 pJ/b for NRZ slow-and-wide VCSEL is an estimate including spatial fan-out assumptions; 0.90 pJ/b for a PAM4 108G VCSEL array is measured, but the full tile is estimated at ~2; Broadcom's 1 pJ/b excludes the DSP; and the 3.5 pJ/b of a 2.5D WDM interposer is 1.5 for the module plus 2.0 for the remote laser.
He then drew a bar chart, stacking each headline number's omitted overhead (SerDes 1.5 + MCC 0.1 + clocking 0.4 = 2.0 pJ/bit) on top in a lighter shade. The result: the two VCSEL options' 0.90 and 1.00 become 2.9 and 3.0, in the same class as the 2.5D WDM interposer (3.5) that originally looked worst. His closing line is worth quoting verbatim: comparisons need boundary labels, not bar heights.
We extended this table to the whole workshop:
On a common yardstick, Ciena's ladder is the most useful, because all five steps use the same boundary: fully retimed pluggable 30 W (18.5 pJ/bit) → half-retimed LRO 20 W (12.5) → linear pluggable LPO 10 W (6.5) → NPO 8 W (5) → CPO 5 W (3). Huawei framed it as three metrics moving together: today's fast-narrow is 40 dB electrical-to-electrical loss, 0.2 T/mm shoreline density and 20 pJ/bit; slow-wide stage two is <5 dB, 3.2 T/mm and 3 pJ/bit. 16x the density, nearly 7x lower energy — at the cost of optical engines wrapped all the way around the XPU.
It's the same disease we discussed in Nature Electronics Opens CPO's Full Books: the biggest information asymmetry in optical interconnect isn't technology — it's that everyone draws the accounting boundary differently.
6. Each Side's Real Leverage: How Fast Materials Can Go, How Wide Light Sources Can Spread
Only after aligning the boundaries does it make sense to compare technology. Both sides have very concrete ceilings.
On the fast side, SOI has topped out. Huawei's Wen Zheng put it plainly: SOI relies on the plasma dispersion effect, its bandwidth is capped by PN-junction RC, and the third generation only adds ~20 GHz on top of the second generation's ~50 GHz. The successor is thin-film lithium niobate (TFLN), which uses the Pockels effect with no junction resistance. On a SiN-SOI+TFLN heterogeneous platform, Huawei achieved 3 dB bandwidth >110 GHz and Vπ < 2 V, cutting phase-shifter power from ~50 mW to ~2 mW. But she also listed four hurdles not yet cleared: CMOS compatibility and contamination risk; 448G may need quartz substrates or suspended structures that conflict with advanced packaging; TFLN is too large to fit in a CPO optical engine; and 12-inch LN wafers and bonding processes simply don't exist yet.
HyperLight's Christian Reimer pushed back on the notion that TFLN is immature: multi-source, geographically diversified LNOI wafers, 6-inch and 8-inch lines, million-unit capacity, ISO certification, Telcordia GR468 qualification; on the telecom side, 130 Gbd DPIQ is shipping in volume with 260 Gbd in development; on datacom, 200G/lane PICs are available (1.6T FRO ~21 W, 1.6T TRO ~12 W, 12.8T XPO ~80 W), and 400G/lane PICs can be driven directly by the DSP, with no external driver. Lumentum offered indium phosphide (InP) as evidence: from 25G/43G NRZ in 2008 to 400G PAM4 in 2024. Harder still were two measured results — a 448 Gbps InP EML developed with Keysight and NTT Innovative Devices, and a 450G InP DFB-MZI demonstrated live at OFC'25.
On the slow side, the constraint is the light source. Lumentum's prescription for slow-wide is the 1060nm VCSEL, and the wavelength history is persuasive: 850nm standardized in 1999; 940nm pushed into high volume by 3D sensing in 2017 (billions of emitters shipped cumulatively); 980nm pushed into high temperature and high reliability by automotive in 2021; 1060nm proposed for high-density interconnect in 2025. The OFC'26 demo showed 32 Gbps/lane, >80 Tbps bidirectional, >1.5 Tbps/mm, <2.5 pJ/bit, BER < 1e-12. But Coherent supplied the physical ceiling: low-current VCSELs measure about 15 GHz at 0.5 mA, and beyond 200G/lane, device optimization is near its limit — and VCSEL links must reach "near-copper stability" to get into the rack.
The micro-ring modulator (MRM) route has the prettiest numbers: Lightmatter's rings are about 15 µm in diameter, and each added wavelength is just one more ring on the bus — wavelengths come nearly for free. EVK50 achieves 16λ bidirectional 56G NRZ, 800 Gbps per fiber, 1 km single-mode, pre-FEC BER < 1e-9 and <3 pJ/bit; EVK100 achieves 16λ 112G PAM4, 1.6 Tbps per fiber; M1000 packs 1,024 lanes of 50G NRZ, >100 Tbps, into a single package. Bidirectional operation halves fiber count, which they estimate yields about 15% network TCO savings.
But Huawei ran the micro-ring numbers the same day — and more harshly than its proponents. To get beyond 400G per fiber, the micro-ring route itself forks: 16λ×32G costs a larger FSR, more insertion loss and area, power uniformity and yield across a 16-wavelength laser, and double the control-circuit area; 8λ×64G costs higher ring bandwidth, coupled-ring designs, higher per-wavelength laser power and a lower-noise TIA.
After Huawei's talk, the chair delivered the most entertaining line of the day: "I love that you're the first person to say in public that 'hanging a bunch of rings on a bus isn't all that great.' Where are the protesters? I'm sure someone is building a 500-line comb laser and saying that solves it. Where are you?" Nobody raised a hand.
Lightmatter admitted the same thing, just phrased differently: slow and wide needs precise, accurate multi-wavelength lasers; standard diode lasers aren't good enough. That's why they build their own GUIDE — 300mm CMOS SOI, 128+ lasers on a single chip, 64+ wavelengths, 0.25 dB power accuracy, 3 GHz frequency accuracy, 0.1 FIT.
Laid flat: the fast side is constrained by materials, the slow side by light sources. Neither is constrained by "optics" itself.
7. The Box Nobody Wants to Discuss: Serviceability
If this session had a villain, it was Chris Cole of Applied Materials. He opened with: "You've already heard six or seven identical presentations, and I won't disappoint you — the technical content is the same. The only difference is that I have conclusions. This field is too polite; people care about others' feelings and don't want to conclude. I have no such constraint."
He first sorted out the taxonomy: NPO is outside the package, CPO inside; CPO further splits into traditional CPO on the main substrate and CIO on a shared interposer. Then he ruled on each: front-panel pluggables will remain an important volume option; NPO is expected to become the next high-volume optics form factor; CPO is a high-performance, closed-ecosystem, relatively low-volume product — quoting an unnamed industry executive, he renamed it "CP0" (CP-zero); and commercially viable CIO packaging is "four, five, six years away, entirely outside the 400GbE deployment window."
He used the NVIDIA 200T ASIC as the comparison: CPO on an organic substrate is about 100 mm square with twelve optical engines around the edge; CIO on an interposer needs only 35 mm, with a die-to-die interface. A 3x area difference — but the packaging technology doesn't exist.
This sparked the fiercest exchange of the Q&A. An audience member countered that hybrid-bonding results of 32 channels, 32 Gbps and 1 Tbps were reported back in 2023, and two years later Jensen Huang announced it as a product — "whoever has the package has the say." Chris Cole replied: "The smartest engineering teams, like NVIDIA and Broadcom, have worked on it for ten years and still haven't shipped in volume." The chair could only laugh: "That's the best coffee-break opener we could have asked for."
Strip out the emotion, and his judgment lands on the same side as Ciena and Marvell. Ciena's data: a 100T ASIC needs an extra 1 kW just to retime optics, so the status quo is technically suboptimal; single-vendor CPO is technically optimal but carries supply-chain risk; only the Open CPX MSA's 6.4T standardized module gets green lights on both technology and supply chain, mapped to a 2027 ramp. Marvell's Lenin Patra singled out serviceability as a decision variable: from pluggable to NPO to CPO to on-die chiplet, integration, power and bandwidth density improve monotonically and electrical distance shrinks from tens of centimeters to microns — but both CPO and on-die chiplets are "not field-replaceable".
OpenAI's Binbin Guan translated this into buyer language. He put the statistical formula for the FIT upper bound on a slide, then drew a step chart of effective compute over time: on failure, compute drops a step and stays low through recovery time; the shaded area is lost effective work. His conclusion was restrained but firm: "OCI's DWDM approach is a viable way to raise per-fiber capacity; but evaluating system reliability needs further failure and recovery analysis." In plain words — slow and wide hasn't delivered field data yet.
This matches the direction we saw in CIOE 2026 芯·光論壇: Why NPO Is No Longer a Stopgap: the industry is moving its bet from "the most power-efficient architecture" to "the architecture you can replace when it breaks."
8. Topologies Are Flattening — the Real Source of Slow-Wide Demand
On components alone, the case for slow-wide is thin. Its case lies in topology.
Credo's Mohsen Asad listed what's happening right now: OpenAI's semi-flat two-tier Clos (electrical), AWS's flat quasi-random graph with passive optical ShuffleBox, Google's Virgo flat high-radix optical fabric, Microsoft's Fairwater single flat network (they coined the term "networking wall"), and Meta's Disaggregated Scheduled Fabric. Google cut hop count from 16 to 7. The reason is all-to-all traffic in MoE and inference — every extra hop is a latency tax, and copper can't claw it back.
He broke the energy budget down segment by segment: rack-level central-switch copper traverses five SerDes stages per crossing, about 14–17 pJ/bit total, with a maximum reach of 1.5–2 m; a flat optical mesh has just two SerDes stages plus two O/E conversions, about 4 pJ/bit, with no retimers and no distance limit. That gap is the reason to push the GPU domain from copper's 72 to 300+. Marvell offered another scale: 72 XPUs per rack with a switched design, 64 with a torus, while optical circuit switching at the PoD level reaches nine thousand chips in one super POD — 144 racks × 96 ICI optical ports = 13,824 fibers, converging onto 48 OCS units.
Closing the session, Xscape Photonics offered the only criterion in the room that can "predict a date": bandwidth × distance. The criterion isn't new — MIT's Kimerling used it twenty years ago to describe telecom's transition from copper to optics (around 10 Mb/s·km); the single-mode fiber transition sits around 80–85 Gb/s·km, and the 2016 shift of data-center scale-out to single-mode crossed at about 100 Gb/s·km. Fifty years, same threshold.
Apply it to scale-up: NVLink2 at 1.2T, NVLink3 at 2.4T, NVLink4 at 3.6T, NVLink5 at 7.2T — copper is approaching the multimode threshold, and the 10-meter-class scale-up roadmap crosses the single-mode threshold at the 12.8T/14.4T generation, around 2028.
Put Section 3's 448G alongside this section's 12.8T and you get the same date: 2027 to 2028. That is the real answer of this debate — not who wins, but that everyone's timeline converges on the same two-year window.
9. What It Means for Taiwan's Supply Chain: Four Links, All at the Bottleneck
Write down all fourteen talks' lists of complaints and you'll find nobody's bottleneck is "optics."
Advanced packaging and interposers. Arista put TSMC's COUPE right on its slide, citing 2021 ECTC data: versus a µbump-based optical engine, COUPE delivers 40% lower power at the same speed and 170% higher speed at the same power. Chris Cole says CIO is four to six years out; Huawei says TFLN won't fit in CPO because of size and RF impedance matching; Arista says native OCI needs 10–20 µm-class bumps and perfect optical alignment — three complaints pointing at the same link.
Fiber coupling, fiber arrays and connectors. Ciena said it outright in Q&A: slow and wide means more fibers, pitch is moving from 125 µm toward 80 µm, and thousands of fibers must be routed off the interposer. Two of the six MSAs (SDM4 MCF, Expanded Beam Optics) exist entirely for volume alignment and automation. The barrier here is manufacturing, not design.
External light sources and ELSFP. This is the most underrated box. OCI, P-CPO and the micro-ring route all need external multi-wavelength lasers with demanding specs. Lightmatter builds its own GUIDE; Xscape uses a Kerr comb source to generate 4 to 128 wavelengths from a single pump laser, and on the show floor demonstrated an 8-wavelength ELSFP compliant with CMIS 5.3 and the 2×4 OCI MSA. Its timeline is concrete: EagleX has accumulated 364,000 device-hours of reliability data and sampled in Q4 2025; FalconX 8's 2×4 OCI version samples in Q2 2026 and the 1×8 CW-WDM version in Q3; the Gen2 16-wavelength version halves power, sampling in July for C-band and September for O-band. Incidentally, the OCI-MSA members listed on Xscape's slide are AMD, Broadcom, Meta, Microsoft, NVIDIA and OpenAI — the buyers are all in.
VCSELs and micro-emitters. 1060nm extends the 3D-sensing and automotive supply chain, with each step using capacity grown by another application before pivoting in; Credo says micro-LEDs are slated for 2027. The key here isn't technical leadership — it's whether you can tap the test, data and manufacturing infrastructure 3D sensing already built.
The time window pulls all the dates together: CPO in scale-out around 2026, in scale-up 2027/28 (Ciena); Open CPX 6.4T standardized module ramps in 2027 (Ciena); OIF and IEEE standardization of 400G/lane has just begun (Qualcomm); 12.8T scale-up crosses the single-mode threshold around 2028 (Xscape); commercially viable CIO packaging is four to six years away (Applied Materials).
This is a two-year window, and it's reserved not for architecture decisions but for manufacturing qualification. For a fuller treatment of how this time pressure relates to the 409.6T wall, see CPO / NPO / XPO Panel: The 409.6T Wall 18 Months Out.
10. Conclusion
The chair complained the poll was "too boring" because most voted for coexistence. But stack up the details of all fourteen talks and coexistence is the only honest answer — just honest for a different reason than most people think: the two routes aren't competing on the same timeline at all.
On the fast-narrow side, InP has measured 448G and 450G single lanes, TFLN has device data at >110 GHz and <2 V, 6-inch and 8-inch lines are running, and 400G/lane PICs can be driven directly by the DSP. Its problem isn't that it can't be built — it's that once built, the electrical signal won't fit into the package. On the slow-wide side, 1.6 Tbps per fiber has run over 1 km of single-mode, 100 Tbps per package has been demonstrated, and <3 pJ/bit is backed by measurement. Its problem isn't that it can't be built either — it's that there's no field failure data yet, and multi-wavelength laser power and wavelength stability are an entirely new yield problem. OpenAI's "needs further failure and recovery analysis" is the politest rejection a buyer can give.
Fast-narrow and slow-wide aren't two routes — they're successive stages on one timeline. Fast-narrow holds until 448G breaks it; slow-wide takes over once packaging is ready; and the crossover falls in 2027 to 2028.
For the supply chain, the actionable meaning is: over these two years, betting on "which modulation" is far riskier than betting on "manufacturing capabilities both will need." Two of the six MSAs are needed whichever side wins; packaging, coupling, test and external light sources are bottlenecks whichever side wins. Roy Rubenstein's line is worth repeating: architecture is a bet; going wider is not.
One indicator to track: the next decisive signal won't be someone showing a higher baud rate or a lower pJ/bit, but whoever first publishes FIT and recovery time for a slow-wide architecture in a real data center. The day that data comes out is the day this debate truly ends.
This article is for technology and industry trend analysis only and does not constitute investment advice.
Related Reading
SEMICON Taiwan 2026 Silicon Photonics Summit, All 14 Talks: The Architecture War Is Over, the Manufacturing War Begins: Section 9's "manufacturing is the bottleneck" gets an even deeper treatment there.
You Can Ban Modules, Not Substrates: Optical Communications' Decisive Battle Has Moved Down to Indium Phosphide: behind Lumentum's 448G InP route lies the supply problem of the entire InP substrate chain.
2026 OCP APAC Summit Full Readout: 24 Sessions Saying the Same Thing: the same-topic roundup from three months earlier — useful for measuring how far industry consensus has moved.
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