Standing in the Light: All 11 Talks from the CIOE 2026 芯·光論壇, and Why NPO Is No Longer a Stopgap (Slides at the End)

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On September 9, 2026, the "芯·光論壇" at CIOE in Shenzhen was packed, with people standing in the aisles. Eleven talks ran from the demand side (Huawei, Tencent, Meituan) through to the supply side (HiSilicon, Marvell, HGGenuine, Lumentum, YOFC). Stack the eleven slide decks on top of each other and you find they are really answering three layers of the same question:

Physically: beyond 224G/lane, copper reaches only one meter. If superpods are to grow across racks and across floors, the only option is to switch to optics. Systemically: chip compute grows with the square of die edge length, while interconnect escape grows only linearly with edge length. That scissor gap is pushing optical interconnect from "front-panel pluggable" to "on-board" and even "next to the chip." Industrially (and this is where the forum truly split): China lacks high-end DSPs and switch ASICs, and NPO happens to be the only path that is "open and disaggregated, reuses the existing supply chain, and can go to 224G right away."

So the forum's strongest consensus surfaced: NPO is no longer "the stopgap before CPO." It has been redefined as a durable form that will coexist with CPO over the long term. Meituan's slide said it outright: "NPO is evolving from a transitional solution to a long-term technology roadmap." HGGenuine's verdict: "NPO covers the mainstream, CPO breaks through at the high end, long-term tiered coexistence." Tencent has already slotted 3.2T NPO volume deployment for 2027 Q1.

But what makes this forum worth writing about is precisely that it did not erase the dissent. H3C's first line on stage was "electrical is the foundation," arguing that NPO "saves nothing it was supposed to save" and that CPO is the only answer beyond 448G. Marvell put up a five-year shipment forecast saying "pluggables remain mainstream; NPO is additive, not a replacement." And HGGenuine laid out a third path, XPO, to let "pluggables hold on for one more generation."

This article covers all eleven talks in full, with every hard number taken from the on-site slides. The final section is STT's take.

1. Opening: Three Numbers That Set the Forum's Temperature

The forum was co-hosted by HiSilicon Optoelectronics and LightCounting, and LightCounting's 曹麗 opened. Her first chart was not about technology. It was about money.

Over the past decade, every time the capex growth rate of North America's four big cloud service providers (CSPs) spiked, it fell back within a few quarters. Not this time: from 2023 Q4 to now, YoY growth has stayed above 60% for twelve consecutive quarters, and Ethernet optical transceiver sales growth is even outpacing capex. On the same chart sat LightCounting's three upward revisions of its Ethernet optical module forecast this year (January, April, July), each higher than the last, lifting the 2031 market size from about $49B to about $74B.

Meituan's 毛明旺 later quoted the written conclusion of the same dataset: Ethernet optical module sales will grow more than 70% in 2026, and the market will reach $80B by 2031. 曹麗 added on the spot that another update is coming at the end of September.

The second number came from 任超 of Huawei's Computing R&D Department in his opening remarks. On stage he declassified a figure that had never been public: a 384-card superpod uses 384 × 7 × 2 optical modules. That works out to 5,376 units, while YOFC's 張磊 gave a more precise delivered figure on his slide: the Ascend 384 superpod uses 384 NPUs, 3,168 fibers totaling 316 km, and 6,912 Xingyun optical modules, achieving a full-mesh NPU interconnect.

任超 was candid about the context: when Huawei decided to build the 384 superpod in 2023, "nobody was particularly confident," because the biggest problem for China's chip industry is the shortage of chips and inadequate process technology, so the only way to stack up large compute was through superpods. To connect that many chips, electrical scaling could not hold up, so in the end everything went optical. He also stated the next step plainly: from 384 to 1K to 8K, the connections will all be optical.

The third set of numbers came from Huawei's 吳雙起, the most complete "money-flow chart" of the whole forum:

Global AI data center investment in 2025 exceeded $500B: Microsoft $80B, Amazon $150B, Meta $60B, Google $75B, Stargate $100B, X.AI $12B
In 2026 H1, NVIDIA alone invested more than $10B in optical interconnect: Lumentum $2B, Coherent $2B, Marvell $2B
Google's monthly tokens processed went from 9.7 trillion in May 2024 to about 480 trillion in May 2025, then past 3,200 trillion in May 2026, a more than 300x increase in two years
Global demand for 800G-and-above optical modules in 2026: more than 100 million units

Put these three sets of numbers together and the forum's tone was set: this was not a meeting about "whether optical interconnect has a chance," but about "which optical interconnect, and when."

2. Huawei's 吳雙起: 224G Is Copper's Physical Finish Line

吳雙起 of Huawei's Cloud & Computing Hardware Department opened with: "I've been at Huawei for over twenty years, always working on optics." His slide deck, "Superpod Interconnect Requirements and Challenges," covered the hardest part of the demand side.

Copper Out, Optics In: Not a Slogan This Time

"Copper out, optics in" has been said in optical communications for a decade, but this time it was quantified.

Citing data from Huawei 2012 Laboratories, 吳雙起 drew the curve of copper reach versus data rate: about 3 m at 56G, about 2 m at 112G, and only 1 m at 224G. At 224G and 1 m, copper insertion loss is 35 to 40 dB, no longer able to sustain a stable bit error rate (BER).

The slide put it bluntly: 224G is copper's "physical finish line" in data center interconnect.

To go further, copper has only two options: add retimers (stacking cost) or use thicker gauge. He showed an AWG table: 8 AWG has a 3.26 mm conductor diameter and 2.061 mΩ/m resistance; 30 AWG is only 0.25 mm in diameter but 338.6 mΩ/m. Once the gauge gets thicker, cable bundles simply cannot be deployed or maintained inside a rack.

As per-lane rates rise, effective electrical channel reach shrinks; 224G is copper's physical finish line (Source: Huawei 2012 Laboratories, NVIDIA)

800G LPO Has Already Demonstrated the Answer Once

吳雙起 treated the 800G generation as an experiment that has already run its course, putting the two 800G SR8 options side by side:

Key metric	800G SR8 LPO	800G SR8 oDSP
Reach	50m–100m	50m–100m
One-way latency	Far below oDSP (exact value masked with "x" on the slide)	~110 ns
Power	~4.x–6 W	14–17 W

What this table shows: remove the DSP and power drops by about 70%, with no penalty on reach or BER. He also noted that 800G LPO paired with VCSELs has pushed the application range "from 50 meters to 100 meters."

We previously broke down the branches of this path in After Copper Gives Out on AI: Seven Paths to Scale-Up Optics and Two Ways to Survive the Bottleneck; 吳雙起's table effectively uses Huawei's own volume data to complete the first leg of the "linear direct-drive" path.

Three Highs, Three Lows: Superpod Requirements, Fully Quantified

吳雙起 broke superpod requirements for optical interconnect into "three highs" and "three lows," each with a numeric target. It was the most concrete requirements document of the entire forum.

Three highs:

High reliability: the reliability target must improve from today's 500 FIT/module @50°C to 30 FIT, a more than 16x improvement. His reasoning was direct: LLM training and inference involve thousands to tens of thousands of chips, and any single link flap causes job rollback and wasted compute.
High bandwidth: per-module bandwidth must shift from "going faster" to "going wider," with WDM eventually targeting 800G per fiber. The cross-section comparison on the slide was interesting: a 1.5 mm × 0.7 mm 32 AWG copper cable carries 8×224G, while single-mode fiber with an 8–10 μm core (125 μm cladding) can carry 8 to 36 channels of 224G.
High density: front-panel width per lane must shrink from 2.8 mm/lane to 0.43 mm/lane.

Three lows:

Low latency: DPO at 110 ns → LPO at <10 ns → NPO at <5 ns
Low power: DPO at 20 pJ/bit → LPO at 5 pJ/bit → NPO at about 3 pJ/bit. He also gave an often-overlooked ratio: optical modules account for up to one third of total equipment power in a network rack.
Low cost: at OFC 2014, someone called for "a $100 100G module" when a module cost $1,200; by OFC 2025 the industry had reached $1/Gbit; the next target is $0.125/Gbit.

Electrical channel length, DSP location and energy per bit across four optical interconnect forms (Source: Huawei, Meituan, Marvell on-site slides)

Module Form-Factor Evolution: NPO from 2026+, CPO Only from 2030+

吳雙起 closed with a form-factor roadmap spanning 1999 to 2030+, split into three eras:

Front-panel module era: from SFP, XENPAK and XFP through QSFP28, QSFP-DD and OSFP, paired with 112G SerDes
On-board optics era (2026+): NPO, paired with 224G SerDes
Chip-level optical I/O era (2030+): CPO / OIO, paired with 448G SerDes, moving toward all-optical interconnect, optical switching and optical computing

One word on the chart was in red: "Leap", placed between front-panel and on-board. Huawei's view is that the 2026 jump is not incremental; it is a discontinuity.

3. Tencent's 姜志濱: The Question Is No Longer "Can It Be Built" but "Can It Be Deployed"

Tencent optical networking expert 姜志濱 reframed the question as soon as he took the stage:

In the first half of the year everyone was still debating whether NPO could be built. Today I want to talk about whether NPO can be deployed.

This was the single most important shift in tone at the forum. Going from a feasibility question to an engineering question means this cloud provider has finished its evaluation, made its decision, and put the timeline on its volume calendar.

Why Tencent Chose NPO Over CPO

姜志濱 presented a four-option, six-dimension comparison table, the cleanest selection rationale of the whole forum:

Option	Interconnect scale	Bandwidth density	Yield & cost	Serviceability	Reach
AEC	Single/dual rack	Low	High yield, low cost	Pluggable replacement	<5 m
AOC	Multi-rack	Low	High yield, moderate cost	Pluggable replacement	<500 m–2 km
NPO	Multi-rack	Moderate	Moderate yield, moderate cost	Equipment-level replacement	<500 m–2 km
CPO	Multi-rack	High	Low yield, high cost	Not replaceable	<500 m–2 km

The conclusion is obvious at a glance: AEC is vetoed outright on "interconnect scale," since it only supports a single rack while superpods are moving from centralized (single-rack designs like NVL144 and NVL576) to distributed. CPO wins on bandwidth density but is red on yield, cost and serviceability. NPO is the only option that is green or acceptable across all six columns.

512-Card Superpod: Two NPO Deployment Forms

Tencent's target topology is clear: a full interconnect for a 512-card superpod using 3.2T NPO.

The network diagram on the slide runs like this: 512 GPUs → electrical shuffle → retimers → 3.2T NPO (×4 per group) → 16 NPO switches (SW0 to SW15). Link rates are labeled 200 Gbps, 100 Gbps/lane, 800 Gbps, and each NPO switch has 102.4T of capacity.

NPO appears in two forms in this system: one is NPO I/O boards breaking out directly from the GPU side, and the other is a dedicated NPO switch. 姜志濱 noted that the switch nodes on the right can actually reuse the earlier 64-card and 128-card rack designs, simply swapping the interconnect from copper to optics.

GPU-side NPO I/O board breakout vs. NPO switch: Tencent's 512-card superpod scale-up network (Source: Tencent on-site slides)

Standardization Has Reached "Light Customization"

The most frequently asked question: do the photonic and electronic chips inside an NPO need to be fully custom? 姜志濱's answer was no.

Both the electrical and optical interfaces of Tencent's 3.2T NPO are standardized, while the internals are disaggregated:

EIC: supports 4- or 8-channel TIAs; driver RF pitch supports both 625 μm and 375 μm
PIC: supports both DR16 and DR16 mirror layouts; EC pitch supports 127 μm and 84 μm

In his words, it is "not clearly different from a pluggable module": the "finger-style pluggable" is simply replaced with an LGA or mezzanine-style pluggable, and little else changes. That is also why he believes module makers should find NPO "relatively easy to master."

Silicon Photonics or VCSEL? Tencent Brought Measured Data

This was one of the few pages at the forum with first-hand comparative measurements.

Eye diagrams: Channel 1 ER = 4.63 dB, TDECQ = 0.9 dB; Channel 2 ER = 4.65 dB, TDECQ = 1.35 dB
BER box plots: the silicon photonics NPO baseline sits at 3×10⁻¹⁰; the VCSEL NPO baseline at 2×10⁻⁸

That is nearly two orders of magnitude apart. 姜志濱's reading was not "VCSEL doesn't work," but that silicon photonics has enough margin to strengthen system robustness. While validating whether the system works, SiPh is the better route; VCSEL still has a lot of headroom for future performance gains.

The Real Challenges: Compression Mounting and Reliability

姜志濱 spent more than a third of his time on two very unglamorous topics.

The first is compression mounting. NPO is secured via LGA and is highly sensitive to clamping force. He showed measured BER versus clamping force: at a PCB warpage point, BER distributions under 5 kg and 10 kg differed clearly; at a normal PCB point, changes in clamping force barely affected BER. The slide's conclusion was direct: PCB warpage points are affected by changes in clamping force. That means NPO EVB design, PCB thickness and support-point layout all have to be redone. The current NPO switch approach ties eight NPOs together into one block, secured with a screw-down pressure plate.

The second is reliability modeling. Since NPO is not yet truly in service, reliability can only be inferred from the failure distribution of pluggable modules. The slide listed six failure categories (optical contamination, component failure, laser, process/adhesive, plug-in failure, fiber cable failure) and mapped each to an NPO mitigation:

Failure type	NPO countermeasure
Optical contamination	Fully sealed housing reduces internal contamination
Component failure	Most control chips move to the host; the module is protected inside the host
Plug-in failure	Heavy cover-plate compression socket design (mechanical fixing replaces hand tightening)
Fiber cable failure	Midplane-free design reduces connector hops
Process failure	Uses BGA packaging, with no adhesive-based coupling
Laser failure	Uses external ELS, pluggable

姜志濱's reasoning: plug-in failures were the largest source of failures, and once NPO replaces manual plugging with mechanical fixing, this category should drop sharply. In addition, NPO modules are installed at the equipment maker's factory and protected inside the host before shipping to the data hall, so they are mechanically secured far better than pluggables during transport and production. His conclusion is that NPO reliability will be "far better than pluggable modules."

But the cost was written on the slide's last line: "No field hot-swap; 3.2T NPO reliability must be driven close to that of the whole system."

How NPO's mechanical fixing and packaging design neutralize the six main failure sources of pluggable modules (Source: Tencent on-site slides)

Timeline

The roadmap on the slide reads:

Date	Milestone
2025 H2	Spec definition (Tencent 3.2T NPO specification)
2026 H1	DVT
2026 H2	PVT
2027 Q1	512-card superpod deployment
2027 Q2	Feasibility analysis report

Notably, 姜志濱 said verbally "real deployment between the end of this year and early next year," slightly earlier than the 2027 Q1 on the slide. We go with the slide. The interconnect equipment was on display at CIOE.

4. Meituan's 毛明旺: AI Networking's Real Problem Is Not Speed but Operability

毛明旺 of Meituan's Infrastructure Department spoke on "Optical Interconnect Practice and Outlook for AI Networks," but the most valuable part was not the speed roadmap. It was his clear explanation of how AI agent workflows hit the network.

Three Numbers That Show This Is Not Linear Growth

About 2.1 years: the build cycle of a GW-class data center
5x per year: growth in compute needed to train large language models
30x per year: growth in LLM context windows

His logic was simple: network plans made today, if extrapolated linearly, risk a fundamental rebuild by next year. Optical interconnect validation and technology readiness must therefore run ahead of data center construction.

Generational Roadmap

Meituan's DCN generation table was the most complete at the forum:

Generation	SerDes	Interconnect	Radix	Optical module
DCN 3.0	25G NRZ	25G DAC/ACC	128×	100G Q28 SR4/CWDM4
DCN 4.0	50G PAM4	200G 1:2 DAC/ACC	64×	400G Q-DD SR8/FR4
DCN 5.0	112G PAM4	400G Q112 SR4	128×	400G Q112 SR4/DR4
DCN 6.0	112G PAM4	800G OSFP 2×SR4	128×	800G OSFP 2×DR4
DCN 7.0	224G PAM4	1.6T OSFP 2×SR4	128×	1.6T OSFP DR8/2×FR4
Future	—	NPO / CPO	—	—

Status: 400G is deployed at scale, 800G is in volume deployment, and 1.6T is being planned.

Agent Workflows Change the Shape of the Network Problem

This was 毛明旺's most insightful page. Traditional LLM inference is "one request, one response, done." AI agent workflows are "continuous loops, autonomous decisions, dynamic execution." Their network demands are completely different:

	Traditional LLM inference	AI agent workflow
Execution mode	Single request/response, stateless	Multi-turn loops, context keeps accumulating
Compute profile	Compute-intensive, GPU continuously loaded	IO-intensive + intermittent compute; GPU idle while waiting on tools
KV cache	Short-lived, released after use	Keeps growing: 100K tokens ≈ 20–50 GB, must persist across steps
Traffic pattern	Short bursts, predictable, easy to schedule	Mixed flow sizes: small tool-call flows (KB-scale) + large KV migration flows (GB-scale), unpredictable and hard to schedule

Three new challenges follow, each with quantified impact:

ECMP routing breaks down: elephant flows saturate bandwidth → tool-call latency spikes → slower responses between agent steps
Scheduler and network are disconnected: inference schedulers only see GPU utilization and KV cache hit rate, not network topology. The result: cross-pod KV cache migration costs tens of GB of overhead and seconds to tens of seconds of migration latency
High network link failure rates: the failure probability of a single module is low, but at system scale the absolute number of failures is high, and agent tasks run for hours, so they cannot tolerate it

Of the corresponding optimization directions, the third is the most interesting: moving from "handle failures after they happen" to "identify early and self-heal," with the goal of catching more than 90% of optical link issues at bring-up and cutting diagnosis time to minutes.

eSR: Pulling Multimode Reach Back Out

On standards, Meituan is working with IPEC to push the eSR family of multimode specs, with a clear goal: extend multimode fiber reach so it stays relevant in scale-up.

Spec	SR (current)	eSR (Meituan's push)
400G SR8 / eSR8	100 m	200 m
800G SR8 / eSR8	100 m	150 m
1.6T SR8	50 m	Targeting 100 m

Measured 800G eSR8 results at 150 m: pre-FEC BER < 1×10⁻¹⁰, post-FEC error free. Each of three technical contributions was quantified:

Lower RMS and higher-order mode energy → reach up 25%
Optimized package thermal stress → system performance up 15%
Optimized system nonlinearity → system performance up 15%

The Slide That Settled NPO's Positioning

毛明旺 showed a slide titled "NPO Has Become a Long-Term Technology Choice." Four statements, each worth quoting in full:

NPO is evolving from a transitional solution into a long-term technology roadmap. Mainstream users have all confirmed NPO's strategic positioning: it balances near-term bandwidth needs with R&D risk control and beats CPO on open architecture, ecosystem maturity and cost control, shifting from a "stopgap" to a major technology path running in parallel with CPO over the long term.

224G/lane is the key technology node. On light sources, ELS leads today's mainstream thanks to its mature ecosystem; on modulators, SiPh MZM/MRM dominates scaled deployment; on packaging, CoWoS is in mature volume production while CoPoS is ramping yield. 224G/lane is the "best window" for NPO adoption.

Operations must shift from reactive to predictive. Once NPO drops front-panel hot-swap, repair time grows from minutes to hours (or days), and the failure boundary expands into a multi-dimensional coupling of "ASIC / package / optical engine / in-chassis fiber / ELS."

Standards should account for the 224G→448G transition. Channel simulations show that versus traditional pluggable channels, NPO shortens PCB traces from 5–8 inches to 2 inches and raises channel margin (COM) from 4.06 dB to 5.15 dB.

On insertion loss, Meituan gave the most intuitive three-way comparison of the forum (all @224G):

LPO/LRO pluggable: typical loss 23–26 dB, four interface loss points
NPO: typical loss 7–9 dB, three interface loss points
CPO: typical loss about 3 dB, one interface loss point

On power, pluggable modules run about 15–20 pJ/bit, while NPO can drop to 7–10 pJ/bit.

Operability Is NPO's Real Bill

毛明旺 laid out NPO's cost honestly: pluggable module MTTR is about 0.25 hours. Once NPO removes hot-swap, board-level and system-level capabilities have to bring repair efficiency back into a controllable range. His proposed three-layer operations framework:

Device and optical path level: collect TX/RX optical power, bias current, voltage, temperature and BER/FEC to spot early signs of degradation such as end-face contamination, temperature drift and shrinking link margin
Board and system level: span OE, ELSFP, connectors, packaging and switch ASIC to achieve lane-level root-cause isolation and multi-vendor fault demarcation
Job and service level: correlate link health with training/inference jobs to enable risk alerts, traffic scheduling, automated diagnosis and self-healing

His closing line was spot on: "Every current optimal solution is the start of the next problem."

5. FiberHome's 邱晨: The Equipment Vendor's Dirty Work, and the "Not a Technology Problem" Conclusion

邱晨, general manager of FiberHome's Computing Interconnect product line, was the only speaker who fully laid out the equipment vendor's perspective. He opened by joking that after nearly twenty years in telecom, always presenting on transport at trade shows, the company now had to create a dedicated "Computing Interconnect product line."

From Scale Across to Submarine: A Reach Hierarchy

FiberHome splits optical interconnect scenarios into four tiers, each with completely different trade-offs:

Scenario	Reach	Equipment form
Scale Across	<80 km	Pluggable coherent modules + 1U/2U box equipment
Metro DCI	300 km	Pluggable coherent modules + box/card-based equipment
Long Haul	2,000 km	Larger coherent modules + multi-slot chassis
Submarine	10,000 km	Large multi-tier chassis

邱晨's core argument: for the past decade optical transport chased "maximum capacity and longest reach per fiber," but for compute the requirement has become a balancing act among reach, power, cost, capacity, density and serviceability. It is not about having it all, but constantly adding and subtracting by scenario.

In submarine systems, power, cost and size barely matter; the goal is to squeeze every slice of spectrum and every meter of reach. Scale Across between data centers is the opposite: the whole band is filled once with almost no per-channel adjustment, so the goal is low cost and simple deployment. Components thought to be obsolete, like AWGs and TFFs, are coming back in this scenario.

Hollow-Core Fiber vs. G.652D, Head to Head

At CIOE, FiberHome showed a live test system: 32 pluggable coherent modules on each end, with two paths in between (hollow-core fiber @50 km and G.652D @50 km) to directly compare latency and performance.

Six hard metrics:

Item	Value
Ultra-high density	25.6T @2U
Ultra-low latency	167 μs @50 km
Ultra-low power	<80 W/T
Simplified deployment	One Fiber One Device
Ultra-low dispersion	≤3 ps/(nm·km)
Ultra-low attenuation	C+L 0.05 dB/km

On the market side: Scale Across has a CAGR above 55% (2025→2030F), clearly higher than other coherent transport markets; the intra-data-center scale-up/out interconnect market is above 40%.

Context Length Determines the Return on Hardware Upgrades

This is a rarely seen table from FiberHome's slides, showing "how efficiently hardware upgrades improve performance at different context lengths":

Context length	Performance gain from hardware upgrade
8K	+20%
128K	+110%
1M	+80%

The takeaway: at the 128K sweet spot, the marginal return on hardware upgrades is highest, and 128K happens to be the mainstream context length for today's agent workflows. In other words, the return on investing in interconnect hardware right now is at a historic high.

The "Not a Technology Problem" Conclusion

When 邱晨 got to NPO, he made the most candid industry call of the forum. His slide had two columns:

Left column, "Technology: optics replacing copper is inevitable":

Copper transmission capability at 224G SerDes
Per-rack power and connection density limits
40% of power and cost is spent "moving data" rather than processing it
"Flat, wide superpods" driven by low-latency needs

Right column, "Competition: using optics to compensate for electronics is inevitable":

Tight supply and high cost of switch ASICs
Domestic PAM4 DSPs remain a bottleneck

The conclusion underneath: "NPO is the clearest intersection of demand in China."

His spoken version on stage was even more explicit: "This is actually not a technology problem; I think it's an industry problem. Right now, the competitive relationship between China and the US means that in China... NPO may not be an intermediate iteration that passes quickly, but within the domestic ecosystem it is truly the intersection of technology and competitive demand."

This was the clearest explanation at the forum of "why China's supply chain is embracing NPO in particular."

FiberHome's Own NPO Switch

Fengine 51.2T NPO Switch: supports 128×400G or 64×800G optical interconnect
Vertically integrated in-house 3.2T optical engine, also supports third-party optical engines
Vertically integrated PM fiber, MPO, shuffle and connectors
Uses domestic 25.6T / 51.2T switch ASICs
In-house x86 control daughterboard and BMC daughterboard
Liquid cooling with air-cooling assist; integrated ASIC + OE cold-plate balancing

But 邱晨 was candid about the difficulties, which closely matched what Tencent described: how to compression-mount sixteen OEs on one PCB, how to ensure reliable contact with the sockets beneath, and how to coordinate PCB routing near the switch ASIC for different OEs in different sockets.

He also dropped a pointed measurement: the same optical engine can show BER two to three orders of magnitude apart when placed in a domestic versus a foreign switching system. The reason is that domestic switch ASICs have weaker drive strength on some ports and huge port-to-port variation, so ASIC, PCB routing and OE design must be iterated together to avoid "long boards crowding long boards, short boards crowding short boards."

Micro LED: The Hidden Bill of Slow and Wide

邱晨 also covered Micro LED, which is essentially another form of NPO: swapping "fast and narrow" (112G or 224G SerDes) for "slow and wide" (e.g., 400 channels × low data rate).

Micro LED's inherent advantage is that the light source and driver can be made together in CMOS, and even the lenses on the emitting surface can be CMOS-etched. But he flagged a commonly ignored cost: today's ASICs are all high-speed designs, so a gearbox for serial-parallel conversion is unavoidable. Once that conversion power is counted, Micro LED's supposed power advantage shrinks a lot. Unless a chip is built specifically for this use case.

The passive side is no small challenge either: traditional NPO uses 12- or 16-fiber FAUs, while 400 channels plus redundancy need at least a 20×20 2D FAU.

His summary offered two predictions: optical interconnect moving down into the data center, the node and the board is an inevitable trend; NPO will accelerate across China's domestic ecosystem, with volume commercial deployment in 2027.

6. H3C's 阮祖亮: The Forum's Lone Dissent: Electrical Is the Foundation, CPO Is the Endgame

If you could only attend one talk at this forum, I'd pick this one. H3C optical system architect 阮祖亮 titled his talk "Electrical as the Foundation, Optics as the Wings," and his first words on stage were:

Why put it this way? Because for all the technology we have, no matter how far optics advances, optics still can't do computation. So in the end, everything still has to be done electrically. If you can't do electrical well, you can't do optics well.

That was an equipment-vendor architect speaking to a room full of optical module makers.

Where Did 2.4T Come From?

阮祖亮 first explained a spec many people find puzzling: why does a 2.4T appear in market forecasts?

The answer is that electrical can't go faster. With modulator bandwidth topping out at 56 GHz and electrical I/O at 224G, overseas vendors proposed a stopgap by changing the modulation format: keeping the physical lanes the same but raising effective bandwidth through upper-layer protocol changes, which works out to 2.4T. His judgment: this is an interim spec between 224G and 448G, and its market will shrink quickly once 448G arrives.

LightCounting's stacked chart supports this: the 2.4T layer only appears in 2028, while 3.2T appears in 2029 and becomes the largest contributor by 2031.

That 228% CAGR

阮祖亮 cited Yole Group's July 2026 forecast, the most aggressive number of the forum:

CPO optical engine revenue: $89M in 2025 → $112.1B in 2031, a 228% CAGR. Within that, scale-up CPO optical engines grow at a 266% CAGR and scale-out at 128%.

His own framing was more conservative: "over 200% growth per year." But he also added an honest caveat: the current AI boom may not be sustainable, with "volatility" ahead in 2028.

He also had a vivid bit of self-deprecation on stage: "Lots of friends in the investment world who never used to look at optics now call me all the time... The market may have placed too high expectations on optical technology, hoping optics can solve every problem. I don't think that's very realistic."

The 224G/lane Loss Budget: Why NPO "Saves Nothing It Should"

This was 阮祖亮's most technical and most damaging section. He began with the 224G/lane loss budgets for each channel type:

Type	Loss budget	Topology
VSR	32 dB	No connector
MR	35 dB	1 connector
LR	40 dB	2 connectors
Linear	22 dB	No DSP

The key is the last row: linear (LPO/NPO) designs have no DSP to regenerate the signal, so the switch ASIC alone has to carry the drive for the entire electrical path, and the usable loss budget is cut in half, from 40 dB to 22 dB.

In his words: "After the DSP regenerates, I can take that signal back to a lossless state and recompute drive strength for the next stage. Linear can't do that; with linear I have to count the entire circuit together."

The challenge isn't the 22 dB figure itself, but that 22 dB has to cover every port on the switch front panel. Front-panel ports sit in three, four or even six tiers, while the PCB is two-dimensional; even populated on both sides it is only two layers, so layer transitions are unavoidable and each one adds signal loss.

There are three fixes: stand the ports up (vertical line cards), fly-over cables, or since the signal you fly out will become optical anyway, why not convert to optics right there? That's NPO.

This is where 阮祖亮's critique lands:

With NPO, every interface you were supposed to save, you haven't saved at all. If you only run straight PCB traces, the loss is linear and can be compensated. It's only at each abrupt port transition that you find signal degradation you can't compensate.

So H3C's conclusion: CPO is the answer for the next generation beyond 448G. He acknowledged NPO's value (serviceability, open disaggregation, the dividends of the domestic ecosystem), but from a purely electrical standpoint NPO does not solve the root problem.

This view and 毛明旺's insertion loss numbers are really two readings of the same reality: NPO's 7–9 dB is a huge improvement over pluggables' 23–26 dB, but still more than twice CPO's 3 dB. Whether you see 7–9 dB as "good enough" or "one step short" decides which side you're on.

We broke down the same tension in 2026 OCP APAC Summit | CPO / NPO / XPO Panel: Not a Roadmap War, but the 409.6T Bottleneck 18 Months Out; that one was in Taipei, this one in Shenzhen, and Shenzhen added one more variable: supply chain self-reliance.

Three Real Uses of OCS, and Its Weak Spots

阮祖亮 spent a good while on OCS, and was more clear-eyed than most of the optimistic takes on the market.

He started with a bucket of cold water: "OCS optical switching sounds nice since we don't need electrical-to-optical conversion, but in reality, at this stage, it still functions as an automated patch panel."

Specs of the two current OCS types:

	3D MEMS	Piezoelectric ceramic
Port count	320 × 320	384 × 384
Wavelength	1260–1625 nm	1260–1625 nm
Insertion loss	1.8 / 3.0 dB	1.5 / 3.0 dB
Crosstalk	−50 dB	−50 dB
Switching time	50 ms	100 ms
Power	50 W	140 W

Google's three uses: backup (fast switchover when a card goes down), smooth upgrades (OCS bridges network segments running at different speeds), and the most discussed, large-scale training. Port counts have evolved from 96×96 → 136×136 → beyond 400×400.

But 阮祖亮 stressed: even if the network outside is all OCS, there are still multiple electrical switching nodes inside the tube. OCS is a re-adaptation of the electrical network, dynamically adjusting topology and routing via SDN; for now, OCS is still a solution that can't do without electronics.

He pointed out two weak spots:

Port sensitivity: as port counts multiply, per-port insertion loss exceeds IM-DD specs. The fixes are Coherent Lite (but higher power on both ends and more latency) or SOAs (but added optical noise, and multi-channel SOAs drive up cost sharply)
Link re-establishment latency: SiPh processes can make the OCS itself switch in nanoseconds, but link re-establishment latency mostly sits in the optical module and the previous-hop switch. Burst mode enables ultra-fast link setup, but currently supports only 10 Gbps

He also gave a clear layering by timescale: OCS for the resource layer (seconds/milliseconds), OFS for the flow layer (microseconds/nanoseconds), OPS for the packet layer (picoseconds). Today's OCS sits only in the top layer.

He closed with an imaginative point: the biggest advantage of SiPh OCS over MEMS is that silicon photonics may one day enable optical computing. If optical computing ever breaks through, combining OCS with SiPh could deliver true all-optical computing and all-optical switching. He added himself: that's a vision.

Why Multi-Core Fiber Is the Answer for OCS

The logic here is elegant. OCS port counts look large (320×320), but each incoming port carries a single path. Google's approach uses FR4 or WDM, but laser count makes it expensive. Multi-core fiber can multiply interconnect density within the same link, with one OCS channel carrying multiple optical channels.

He also noted another benefit of multi-core fiber: in in-equipment interconnect scenarios like CPO / NPO, multi-core fiber can significantly reduce fiber routing cost and deployment difficulty. And he pointed out this standard is led by Chinese vendors, "showing that Chinese companies going global have more and more say."

As for Micro LED, 阮祖亮's stance was "not entirely bearish, but less rosy once you run the numbers." Besides flagging the gearbox power issue like 邱晨, he raised an overlooked link: the short-reach imaging fiber Micro LED needs is extremely expensive on today's market, because its original applications demanded reliability and skin-friendliness, and using conventional telecom fiber for this job is "using a cannon to kill a mosquito."

The numbers on his slide: with imaging-fiber solutions, Micro LED today can carry 2G bandwidth only 20 meters, short of the 30-meter cross-rack requirement ahead, and the fiber is bend-sensitive. Fiber design requirements: support more than 400 lanes of synchronous transmission, meet data center bend-radius requirements, meet loss targets over 30–50 meters, and match the per-area density of today's DR8 solutions.

His final line was the best closer of the entire forum:

Every problem looks like an optics problem, but in the end it comes back to electronics. Yet to fully exploit the advances in electronics, we still have to rely on optics, and amplify them as much as possible.

7. HiSilicon Optoelectronics' 邵海峰: Breaking NPO Down to the Device Level, Then Solving It Piece by Piece

The first speaker of the second half was 邵海峰 of Huawei HiSilicon Optoelectronics. If the first half was about "what's needed," the second half was "how to build it," and HiSilicon's talk had the highest technical density of the forum.

The Scissor Gap: One Chart That Shows Why Optics Is the Only Answer

邵海峰 used a normalized growth curve (2020 = 1) to show the root of the problem:

Generation	Per-chip compute (FP8)	Chip-to-chip bandwidth (NVLink)
A100 · 2020	1	1
H100 · 2022	3.2	1.5
B200 · 2024	7.2	3
Rubin · 2026+	25	6

Over six years, compute grew 25x while interconnect bandwidth grew only 6x. His physical explanation: compute scales with the square of die edge length (area), while interconnect escape scales only with edge length (shoreline). That's why the scissor gap keeps widening, and why "stacking more chips" can't fix it.

He also laid out the pressure from the model side: GPT-4 at 1.8T parameters, GPT-5 at 2–4T, GPT-6 Astra approaching 10T; on the domestic side, Kimi K2 at 1T / 384 experts, Kimi K3 at 2.8T / 896 experts, DeepSeek V4 pro at 1.6T / 384 experts, Qwen 3.8-Max at 2.4T / 512 experts. MoE architectures spread experts across different cards and activate only a few per computation, which means every inference requires hundreds of cross-chip all-to-all communications.

The superpod scale race was also laid out:

Year	Huawei	Vendor N	Vendor G
2025	A3: 384 cards	72 cards	64 cards
2026	950: 8,192 cards	144 cards	2,048 cards
2027	>10,000 cards	576 cards	9,600 cards

FOM: Four Optical Interconnect Metrics in One Formula

邵海峰 proposed a framework I think the whole industry should borrow:

FOM ∝ [ bandwidth density (Tbps/mm) × reach (m) ] / [ energy per bit (pJ/bit) × latency (ns) ]

Each metric maps to a system problem:

Bandwidth density: how much bandwidth each millimeter of die shoreline can fan out, which determines whether interconnect can keep scaling with compute
Energy per bit: determines whether the optical engine can dissipate its heat in an extremely small space
Reach: determines whether the network can span racks and floors, setting the physical boundary of the high-speed interconnect domain
Latency: determines the weakest-link effect on compute waits and cluster synchronization, mapping directly to TPOT and TTFT

Viewed through this FOM, the evolution of optical interconnect is a trajectory toward "higher density, lower energy, lower latency":

Path	Rate	Efficiency	Density tier
Traditional pluggable	400G→800G→1.6T→3.2T	25+ to 20 pJ/bit	Low (front-panel limited)
LPO linear drive	800G→1.6T	~10 to 7 pJ/bit	Low
NPO / CPO	3.2T / 6.4T–7.2T	~7 to 5 pJ/bit	High (on-board)
Extreme architectural fusion	>16T	<1 pJ/bit	Ultra-high (ASIC edge)

The last tier splits into two sub-paths: Slow and Wide (N × 64G) and Fast and Narrow (36 × 448G).

Channel count, per-lane rate and material platforms for the Fast & Narrow and Slow & Wide paths (Source: HiSilicon Optoelectronics on-site slides)

A3 to A5: HiSilicon Has Already Run Two Generations on VCSEL

Huawei's A3 superpod (CloudMatrix384) uses HiSilicon's in-house 400G SR8 Xingyun optical modules, built on 50 Gb/s VCSELs from a 6-inch GaAs IDM platform, with reach of 200 m or more, and has been running in production for a year.

Huawei's A5 superpod upgrades to 800G SR8 Xingyun optical modules with 100 Gb/s VCSELs, the industry's first use of multimode VCSELs in an LPO architecture. The gains were shown directly on the bar chart:

Latency: from 110 ns for oDSP modules down to 10 ns for LPO modules, a 90% reduction
Power: down 60%

The moderator made a sharp comment: it's not that people can't see VCSEL's cost and power benefits; the worry is usually VCSEL performance. HiSilicon's talk used volume data to knock out half of that doubt.

The 200 Gbps VCSEL breakthrough data was also on the slide: 40 GHz bandwidth (S21 @9 mA), wear-out lifetime over 10 years @60°C / 9 mA, and back-to-back BER of about 5×10⁻⁹, about 1×10⁻⁸ after 30 m of fiber.

3.2T and 7.2T: Two NPO Optical Engines

3.2T VCSEL optical engine: 32 × 112G, ultra-low power of 24 W, OIF form-factor compatible. It uses 112G VCSEL/PD arrays plus a 112G high-speed linear oRFIC.

7.2T SiPh high-density optical engine: 36 × 224G, integrated light source. The roadmap advances on three fronts at once:

Today	→	Next generation
224 Gbps, SiPh	→	448 Gbps, SiPh / TFLN / EML
36 channels	→	72 channels
Integrated high-power light source (CW laser)	→	Heterogeneously integrated silicon-based light source

Integrated Light Source: HiSilicon's Boldest and Most Notable Move

This is, in my view, the most important technical divergence of the entire forum.

The industry mainstream uses an external light source: because of concerns about high-power laser reliability and performance degradation at high temperature, the high-power source is packaged as an EML-like module outside the panel and coupled into the SiPh engine via PM fiber. HiSilicon builds the light source right in, with no external laser module and no PM fiber; the slide calls it Hi-ONE / All in One.

Doing this means solving three problems, and HiSilicon gave data for all three:

First, high-temperature performance. Working from first principles, HiSilicon chose aluminum quantum wells (AlGaInAs, labeled AlQ on the slide) for its lasers rather than the industry-mainstream phosphorus-based material (InGaAsP, labeled PQ). The rationale is that AlGaInAs's band structure gives better carrier confinement at high temperature. The slide directly compared the power conversion efficiency (PCE) of the two at 75°C and close to 200 mW, with AlQ clearly ahead at high current. For NPO, where high temperatures are unavoidable, this is decisive.

Second, reliability. This is aluminum materials' traditional weak point and an industry-wide challenge. HiSilicon showed measured power-change curves over 10,000 hours, staying within the ±10% inner threshold throughout, far better than the ±20% outer spec.

Third, high single-mode yield. Test conditions were 80°C, 200 mA, with a 3D spectral plot showing wavelength stability (starting at 1304 nm).

The industry's XPO + external light source approach (16 external laser modules + PM fiber) versus HiSilicon's Hi-ONE integrated light source architecture (Source: HiSilicon Optoelectronics on-site slides)

400G/lane: HiSilicon Bets on Four Material Platforms at Once

Going from 7.2T to 16T, the Fast & Narrow path has to solve 400G per lane. HiSilicon laid out bandwidth data for four modulator options at once:

Option	Bandwidth
Beyond 200G SiPh	3dB BW >70 GHz (targeting 400 Gbps)
400G EML	Bandwidth >110 GHz
400G InP MZ	Bandwidth >110 GHz
400G TFLN	Bandwidth >110 GHz (industry-first TFLN + SiN/SOI/Ge hybrid integration platform)

And the material platform matrix maps out like this:

Material	100 Gbps/lane	200 Gbps/lane	400 Gbps/lane
GaAs	VCSEL	VCSEL	—
InP	EML	EML	EML, InP MZ
SiPh + TFLN + InP	SiPh MZ + CW	SiPh MZ + CW, MRM + Comb	SiPh MZ + CW, TFLN

The industry implication of this table is direct: HiSilicon isn't betting on one path; it builds all four platforms (GaAs, InP, SiPh, TFLN) in-house and lets the system side decide which to use. This is a classic IDM playbook, and the only option when external supply is not guaranteed.

Slow and Wide: Microrings and New Light Sources

The other path lowers the per-channel rate and increases spatial parallelism. HiSilicon's bets here:

Comb light source: 200 GHz channel spacing, 10 wavelengths, 8–10 dBm per wavelength
PCSEL light source: >400 mW @O-band, divergence angle <1°, low RIN, narrow linewidth, high SMSR
Microring modulators (MRM): coverage from 25G, 32G and 64G up to 200G; integration roadmap 32G×8 → 64G×8 → 64G×16
The 200 Gbps high-speed microring already shows a 224 Gbps PAM4 eye diagram

"Eliminating SerDes, integrating system to chip" is the keyword for this path: the XPU or switch ASIC connects directly to a Slow and Wide optical engine via C-Link, stacking up bandwidth through optical WDM.

HiSilicon's overall rate roadmap fits on one chart: 800G → 1.6T → 3.2T → 6.4T → ... → 25.6T, mapped to four technology paths: oDSP direct drive, LPO linear drive, NPO/CPO high-density optical engines, and S&W extreme fusion.

8. Marvell: The Global View: NPO Is Additive, Not a Replacement

The value of the talk by Marvell VP of Product Marketing Lian Qin is that it was the only one at the forum framed from the global market rather than the Chinese market. And its conclusions were noticeably milder.

First, Unifying the Definitions of the Scales

This was necessary, because the first seven speakers didn't use these terms entirely consistently:

Tier	Scope	Name	Characteristics
Tray scale	Between trays	—	Extreme performance, lowest latency, highest bandwidth, Dragonfly topology
Rack scale	Within a rack	Scale up	Vertical scaling; system acts as a single unified fabric
Pod scale	Across racks	Scale out	Horizontal scaling, millisecond latency, distributed workloads
DC scale	Across data centers	Scale across	Regional scaling, connecting geographically distributed data centers

Marvell's corresponding product lines: Marvell Aquila (O-band coherent-lite, 2–20 km), Marvell Ara (1.6T PAM4 3 nm DSP, billed as the industry's first 3 nm solution), and Marvell ACC / AEC (copper PAM4, up to 5 m).

Latency requirements and interconnect technology choices across four tiers, from tray to cross-data-center (Source: compiled from Marvell, Lumentum and HGGenuine on-site slides)

Three Form Factors, Three Lines of Trade-offs

Marvell's comparison table is simpler than the Chinese vendors' versions, but the conclusion is just as clear:

	Pluggable	NPO	CPO
Channel loss	2X	1X	0.5X
Power	TRO 10 pJ/b	5 pJ/b	5 pJ/b
Serviceability	Best	Better than CPO	Worst
Market position	Scale-out mainstream	Scale-up mainstream, bridge to CPO	Scale up

Scale-Out: TRO Leads at 1.6T; Coherent-Lite Is the Wildcard at 3.2T

Marvell's scale-out view was quite specific, with baud rates and efficiency for each:

Solution	Baud	Efficiency	Status
800G (8×100G/λ PAM4)	53 GBaud	<16 pJ/bit	In volume deployment now
1.6T (8×200G/λ PAM4)	106 GBaud	<14 pJ/bit	First deployed 2025
3.2T (8×400G/λ PAM4)	224 GBaud	—	OFC'25 demo
800ZR Coherent	118 GBaud	~35 pJ/bit	—
1600ZR Coherent	~240 GBaud	—	—

The reach boundaries are the key: 3.2T PAM4 only reaches about 500 m, while 1.6T PAM4 reaches about 3 km and 800G PAM4 about 10 km. That means if you still want 2 km of coverage inside the data center at 3.2T, coherent-lite has to move from outside the data center to inside it.

Lian Qin spelled out the trend on stage: pluggable PAM technology only reaches 500 m at 3.2T and above, so covering two kilometers means considering coherent-lite inside the data center.

He also gave the current mix in the 800G generation: about 95% FRO and 5% LPO. Then he made what I consider one of the most important causal inferences of the forum:

Don't underestimate that 5%. LPO's success gives NPO very strong technical backing. Without LPO in deployment, people would have doubts about NPO's reliability and feasibility.

In other words, 800G LPO's 5% share is the reason NPO got its ticket in.

For the 1.6T generation, Marvell is betting on TRO (retimed): 15 W versus 24–25 W for FRO, with BER of 10⁻¹¹ being sufficient, and 1.6T TRO expected to grow more than 50%.

Scale-Up: Going from Rack to Row Is the Disruptive Opportunity

Marvell's scale-up analysis was the most commercially insightful part of the talk:

Stage	Scale	Connectivity	Rate
In-rack scale-up	Hundreds of XPUs	Copper, ACC, AEC	224G → 448G
Cross-rack scale-up	More than 1,000 XPUs	Optics	224G → 448G

He cited NVIDIA as an example: NVL72's scale-up capacity is 9x its scale-out; at NVL576 the ratio becomes 18x. 72 GPUs can still be handled with copper within one rack (about 5,184 copper connections in the rack), but 576 GPUs need eight racks, and the distances between racks rule out copper.

The form-factor shift in the scale-up market looks like this: no NPO/CPO at all at 100G/lane; it starts appearing at 200G/lane; at 400G/lane it is already more than half. Passive copper's share declines as lane rates rise.

"Additive, Not a Replacement"

Of Marvell's five key takeaways, the third and fifth are the most worth remembering:

AI drives optical connectivity demand in both scale-out and scale-up
Pluggable modules target scale-out; NPO targets scale-up
Scale-out is driven by 1.6T FRO/TRO; at 3.2T, coherent-lite enters the data center
The scale-up NPO ecosystem and commercial market are ready
Marvell offers a complete EIC portfolio for scale-out and scale-up

And the line Lian Qin added verbally was the forum's most important qualifier on NPO:

Scale-up isn't eating pluggables' share. It's additive.

He also candidly listed the three main challenges for NPO/CPO deployment: manufacturing complexity (precise optical alignment and fiber attach across more channels, yield and packaging complexity), reliability and thermal management (more channels under high temperature and vibration, with NPO/CPO closer to the ASIC), and serviceability (NPO sits inside the line card; even in a CPX socket, replacement is still inconvenient).

The four corners of ecosystem readiness were named too: CPX MSA (announced at OFC 2026, with Samtec / Molex / TE supplying packaging), PIC (major module makers have their own PICs; merchant PICs come from Xphor and Silith), EIC (Marvell and Semtech supply high-speed TIAs and drivers), and module makers (Terahop, Eoptolink, Coherent, CPT, Accelink and HGTECH have all launched NPO projects).

Further reading: Earnings Highlights: Marvell (MRVL) | Q2 FY2027: FY2028 Target Jumps to $18B, and the Biggest Upgrade Comes from a Business That Didn't Exist a Year Ago.

9. HGGenuine's 許文雄: The Standards Timeline, and XPO as a Third Path

許文雄, standards department manager at HGTECH, has led the drafting of more than forty domestic and international industry standards, so this talk's value lies in something others can't offer: the standards timeline. The actual title on his slide was "CPO/NPO/XPO Multiple Paths: Reshaping Next-Generation Optical Connectivity for AI Computing Centers."

Generation Jump Table

Item	Current generation	Next generation
High-speed SerDes	212.5G-PAM4	425G-PAM4
Modulator technology	Silicon Photonics	InP, TFLN
OSFP module	(8×200G) 1600G	(8×400G) 3200G
Form factor	OSFP (8 lanes)	High-density (64 lanes)

The last row is the biggest jump: from 8 lanes to 64 lanes, this is no longer the same kind of module.

448G: PAM4 or PAM6?

This is a rarely discussed but extremely important divergence:

Dimension	448G PAM4	448G PAM6
Baud rate	≈ 224 GBd	≈ 174 GBd
Device bandwidth pressure	High	Medium
SNR / linearity requirement	Medium	High
Industry maturity	Higher	Lower
DSP/FEC complexity	Lower	Higher

The slide's conclusion: PAM4 continues the existing industry ecosystem but puts significant pressure on device bandwidth; PAM6 sharply lowers baud rate requirements but is more sensitive to SNR and linearity. The Nyquist frequency comparison is brutal: 106.25 Gbps maps to 26.5625 GHz, 212.5 Gbps to 53.125 GHz, and 425 Gbps to 106.25 GHz.

This Power Table Makes LPO's Real Value Clear

Architecture	100G/lane (800G module)	200G/lane (1.6T module)
DPO	15 W	26 W
LRO	9 W	18 W
LPO	8 W	10 W

But 許文雄 poured an honest bucket of cold water on stage:

As a module maker, we can say our cost is down and per-module power is down, but when you look at the whole link, the benefit isn't actually that large, because your ASIC also has to drive harder and burns more power.

This came from a module maker itself, which gives it special weight. Part of the power LPO saves is simply shifted from the module to the switch ASIC. The slide had one more line: full-link cost analysis, "50%? 20%". He put that question mark there himself.

As for the industry's overall efficiency trajectory, transceiver energy per bit from 2016 to 2026 went 38 → 30 → 27 → 22 → 20 → 17 pJ/bit, while switch capacity went from 3.2T to 102.4T over the same period.

The Full Landscape of 1.6T Reach Specs

Spec	Reach	Light source
SR	50 m	850 nm VCSEL
DR	500 m	1310 nm DML/EML/SiP
FR	2 km	1310 nm
LR	10 km	1310 nm
ER	40 km	1310 nm
OIF 400ZR	120 km	1550 nm IQ MZM
OpenZR+ / ITU 400G	500 km	1550 nm

IEEE 802.3dj draft 3.2 is already mature, specifying CR/DR/FR/LR/ER; 802.3ds is still debating 860 nm vs 1060 nm.

NPO Standards: Four Organizations on Strikingly Similar Timelines

This was the most information-dense page of the forum, and something only a standards department manager could present:

Organization / project	Milestones
OIF — 12.8T NPO (covering 6.4T & 7.2T)	Project start 2026.5 → Baseline 2026.11 → Ballot 2027.5 → Publication 2027.8
IPEC — 7.2T NPO	Project start 2026.4 → Standard published 2027.6 → Demo & Test 2027.9
Open AI Infra (CCC) — 6.4T/7.2T NPO	Project start 2026.7 → Standard published 2026.10 → HD Spec 2027 Q1 → Volume commercial deployment 2027 Q2 (currently v0.7)
ODCC — 6.4T/12.8T UPO	UPO 1.0 published 2026 Q3 → 6.4T samples 2026 Q4 → 6.4T volume production 2027 Q2 → 12.8T (448G) definition 2027 Q3 (currently v0.95)

許文雄's own verdict: "Highly converging timelines, fragmentation, overlap and competition."

He also made an important observation: standards teams in China are moving faster than those overseas. The reason is that end customers keep pushing standards into deployment, making the ecosystem active and open. On the OIF side: the ELSFP spec is published, the 3.2T OE spec is published, and the 6.4T NPO spec project has been approved.

The Essential Difference Between CPO and NPO

許文雄 gave a crisp definition: the essential difference between CPO and NPO is whether the optical engine and the ASIC share a substrate.

	CPO	NPO
Signal integrity	Best	Good
Serviceability	No hot-swap, hard to cool	Engine is pluggable, heat sources distributed
Ecosystem / supply chain	Closed	Open
Volume manufacturing	Hard to mass-produce at scale	Reuses the existing mature supply chain

On socket form, China favors the 224G LGA socket while overseas players favor CPX (mezzanine). The two mezzanine sizes are 25.3 × 18.9 mm (6 differential pairs) and 29.6 × 16.5 mm (8 differential pairs). His view: the LGA interface will reach commercial deployment faster; the MEZZ-CPX approach depends on sample timing.

2030 Shipment Mix: One Table Decides Everything

This is LightCounting's forecast of 2030 port composition by speed, and the most investment-relevant table of the forum:

Port speed	Total	Retimed TRX	LPO	CPO
800G	44 M	85%	11%	4%
1.6T	93 M	61%	30%	9%
3.2T	51 M	29%	20%	51%

This table quantifies "tiered coexistence": at 800G, pluggables still hold 85%; at 3.2T, CPO flips to 51%. Each generation has a different answer, and all three options coexist in every generation.

Other market figures: AI optical modules will exceed $20B by 2030, 7x the 2021 level; AI first surpassed non-AI applications in market size in 2024; NPO/CPO is expected to deploy at scale in 2027.

XPO: The Third Path for Pluggables

If NPO is "moving onto the board" and CPO is "moving into the package," XPO is "staying on the front panel, but completely rebuilding it."

12.8T XPO specs:

64 × 200G PAM4 channels, 12.8 Tbps per module
With 400G signaling, a single module can reach 25.6 Tbps
Integrated liquid cooling, with cold plates in direct contact cooling both upper and lower PCBs, supporting up to 400 W of heat dissipation
48 V host power, with voltage conversion inside the module

Scenario coverage: Scale Up (<100 m, SiPh baseline FRO/RTLR/LPO), Scale Out (500 m–10 km, SiPh and EML), Scale Across (80 km + full coherent ZR).

許文雄 specifically clarified: XPO is not meant to compete with CPO/NPO for the high-density slot; it is "the next generation of pluggable optical modules," complementing scenarios rather than replacing existing paths. XPO v1.0 was released to customers and peers in August 2026, and the MSA has 20 members, including Accelink, Coherent, Lumentum, Marvell, Molex, O-Net, Source Photonics and Terahop.

The division of labor among the four major MSAs was also laid out:

MSA	Key members	Positioning
XPO	20 optical module and connector makers	12.8T liquid-cooled pluggable
OCI-MSA	AMD, Broadcom, Meta, Microsoft, NVIDIA, OpenAI	Microring resonators + external light source, supporting NPO/NPC/CPC/CPO
OPEN CPX MSA	Ciena, Coherent, Marvell, Molex, Samtec, Terahop, Accton, Intel, TE	6.4 Tbps pluggable connector, targeting 200G/lane
400G Optical MSA	Broadcom, Cisco, MACOM, NVIDIA, Semtech	400 Gbps IMDD PAM4 optical links

One look at the OCI-MSA member list tells you the hyperscalers have all lined up behind "microrings + external light source."

許文雄's verdict came in four sentences:

CPO/NPO/XPO multiple paths run in parallel; NPO is the optimal solution before CPO scales, with CPO as the ultimate trend for deployment choices; XPO, with high density, native liquid cooling and hot-swap, becomes the near-term mainstream; standardization of NPO's key technology paths has largely converged.

10. Lumentum: The Real Bottleneck Isn't the Architecture, It's the Laser

The talk by Lumentum Senior Director of Product Line Management Mari Fukazawa had the fewest numbers of the forum, but carried the most weight.

The moderator set the context in the introduction: in the first half of this year, NVIDIA invested $2B in Lumentum. Her talk, from start to finish, answered one question: why that money went there.

Positioning Made Clear from the Start

She opened by saying the talk would not focus on a single product, but on how AI infrastructure is changing optical connectivity, and why "scalability and manufacturability" are becoming as important as component performance.

Her view on architecture matched the forum's mainstream, but with a more neutral tone:

The message here is not that one architecture will replace all others. Different architectures are more likely to coexist, depending on cost, reach, sustainability and application.

And the five common requirements no architecture can escape: high speed/high bandwidth, high output power/high efficiency, thermal management, reliability, and manufacturability at scale.

CW Lasers: Framing "More Power" and "Smaller Size" as One Trade-off

Lumentum turned CW laser requirements into a mapping table, with each market trend tied to a device requirement:

Market / architecture trend	Laser requirement	Technical focus
Higher density	Higher output power	High-power operation
Constrained optical footprint	High power in a smaller volume	Power-size optimization
Power / thermal limits	Higher efficiency	Optical and electrical efficiency
Stable operation with less redundancy	Kink-free operation / high SMSR	Stable single-mode operation
NPO / CPO integration	High-temperature operation and reliability	Thermal robustness and reliability

The fourth row deserves attention: she noted that AI cluster data centers have less redundancy than traditional data centers, meaning a single component failure has more severe consequences, so the kink-free operating range must be widened and high SMSR maintained.

The fifth row echoes HiSilicon's point: LPO and CPO will operate close to heat sources, so high-temperature operation and long-term reliability are prerequisites, not nice-to-haves.

The summary line on the slide put it well: CW lasers must deliver more optical power without adding footprint or thermal burden.

Differentially Driven EML: The Answer for 400G/lane

This was the one technical detail Lumentum went deep on, and the solution is elegant.

The problem: as data rates rise, EMLs need more bandwidth, but bandwidth and extinction ratio (ER) trade off: push bandwidth up and ER drops. At the same time, as electrical interface speeds rise, common-mode noise can no longer be ignored.

A conventional single-ended EA-DFB: the DSP produces a differential pair (V_OUT+ and V_OUT−), but a single-ended EML uses only one of them, so half the electrical power is simply wasted.

A differentially driven EA-DFB applies both electrical signals to the EA modulator, so the effective drive voltage becomes V_diff = V_OUT+ − V_OUT−, doubling the swing. Two benefits:

Larger swing improves extinction ratio → breaks the ER-bandwidth trade-off
Positive and negative signals cancel → suppresses common-mode noise

Mari Fukazawa's conclusion on stage was crisp: for 400 Gb/s, the differentially driven EML is the best solution.

From Component Performance to Manufacturability: Four Pillars

The second half of the talk didn't cover technology at all; it was about capacity. Her argument: component performance is only half the story; manufacturing variability and scalability matter just as much.

Four pillars:

Yield (yield stability): performance distributions must be compatible with production guard-bands. If yield isn't stable, shipments can't be stable
Fungibility: different architecture choices mean the product mix will keep shifting, so production lines need agility and adjustability, sharing processes across multiple businesses and products
Scalability: back-end processes such as testing and visual inspection must be streamlined
Reliability: there will be an enormous number of optical connections in the field, so even a tiny failure rate becomes significant

Capacity: Four Fabs Expanding at Once, Plus a Newly Acquired One

Lumentum's InP capacity footprint: Sagamihara / Takao (Japan, main site), San Jose (US), Caswell (UK) are all expanding, plus the recently announced acquisition of Greensboro, NC (US, from Qorvo, including the engineering team). The new fab starts producing wafers in CY28.

But she stressed something important: expanding capacity isn't just adding tools or lines. "EMLs and laser chips are among the hardest semiconductors to produce," and Lumentum has 30 years of experience and accumulated know-how.

This echoed what the moderator said in the wrap-up, which I consider the sharpest industry judgment of the entire forum:

Silicon photonics is very hot lately, so hot that some say in the future everything can use SiPh, light-source supply won't be a problem, and we won't depend on the traditional optoelectronics giants. There's a huge misunderstanding here: silicon photonics can't even emit light. So even if you use SiPh in the future, you'll find you still need InP-based light sources, and semiconductor lasers will become the industry's bottleneck.

We've broken this down in both [CPO Breakdown 3/6] CPO's Most Fragile Link Is the Laser and They Can Ban the Modules, but Not the Substrate: Optical Communications' Decisive Battle Has Moved Down to InP. The Shenzhen forum effectively confirmed it again from another angle.

Further reading: Earnings Highlights: Lumentum (LITE) | FY2026 Q4: Revenue Doubles, Gross Margin Breaks 50% Early, and the Laser Leader Turns "Optics In, Copper Out" into Financials.

11. YOFC's 張磊: The Fiber-Side Answer, and That "Historic Mission"

The closing talk came from 張磊, manager of YOFC's Fundamental R&D Department and general manager of its hollow-core fiber product line. His first words on stage were candid: "Since I'm last, there's a lot of pressure."

But this was actually the most data-solid talk of the forum, because fiber is the only link that is already running in production with real delivered mileage.

First, Finish the Money Math

YOFC's capex forecast was more detailed than any other at the forum:

Year	Combined capex of the top five	YoY growth
2024	$261B	—
2025	$449B	+72%
2026E	$805B	+79%
2027E	$1.1T	+37%
2028E	$1.35T	+23%

2026 guidance by company: Amazon $200–220B, Alphabet $195–205B, Microsoft $185–190B, Meta $130–145B, Oracle $40–50B.

Cumulative global AI infrastructure investment for 2026–2030 is forecast at $5.5T (J.P. Morgan, up $400B from its prior estimate). The optical module market goes from $6.25B in 2023 → $25.8B in 2029.

Density: The Most Urgent Issue on the Fiber Side

張磊 broke the problem into four common bottlenecks: power, density, bandwidth and latency. On density, his numbers had the most impact.

Front-panel density:

Dimension	QSFP-DD/OSFP	MPO-12	MMC-32 (VSFF)
Port pitch	22.3 / 11.1 mm	3.8 mm	1.3 mm
Faceplate size	24.3 × 17.2 mm	12.8 × 9.4 mm	4.2 × 9.6 mm
Ports per 1U	32–36	72	264 (×3.7)
Fibers per 1U	256–576 fibers	864 fibers	6,336 fibers (MMC-24)

32 × 1.6T / 1U = 51.2 Tbps, with 23–25 W per module; densely packed ports block airflow, so thermal power density and faceplate layout must be co-designed.

CPO's gain here is quantified: the electrical signal path shrinks from 30 cm to 4 cm, and per-port power drops from 30 W to 9 W, a 70% reduction.

Fiber consumption:

Scenario	Fibers per rack	Multiple
Traditional cloud rack	40–80 fibers (20–40 cables)	1×
AI computing center	800–1,000 fibers	10–17×
High-end AI cluster	3,600–7,200 fibers	36×

A 10,000-GPU cluster needs about 200,000 fibers for internal interconnect; a single campus can reach millions. Optical modules per GPU have grown from 1.6 to 5 units (H100 at 1:3, B300 at 1:4.5, ASICs up to 1:8).

Fiber counts in inter-building cables are also stepping up: 1,728-fiber cables (only 19.8 mm in diameter) are in commercial use at scale, 3,456-fiber cables are in volume deployment, and 6,912-fiber cables are becoming mainstream for AI campuses, with 13,824-fiber cables beyond that. Global fiber demand in 2026 exceeds 670 million fiber-km, and data center fiber demand is growing 69% YoY.

Latency: The Physics Dividend of Hollow-Core Fiber

This section is YOFC's real trump card, with a complete chain of argument.

The problem: how latency-sensitive is cross-data-center distributed training? The slide cited simulation results from an arXiv paper: as latency grows from within one data center to 40 ms, average training iteration time is amplified by up to about 9x. In a 1,000 km cross-region scenario, the training time multiplier drops from 26x with SMF to 18x with HCF.

The physics: light travels at 0.67c in a glass core and 0.99c in an air core. The difference translates to:

About 33% lower propagation latency
About 1.5 μs saved per kilometer
About 120 μs saved one-way on an 80 km cross-campus link

The deployments: this is the most convincing part. YOFC has delivered 18 hollow-core fiber links, 15 of them in China (including Hong Kong). The timeline runs from a 10.3 km link in Dongguan in June 2024 to August 2026, with the longest being 413 km in Wuhan in January 2026, plus 114 km overseas, 95 km in Hangzhou, 41.87 km in Hong Kong and others.

Hollow-core performance records keep falling too (cited here from H3C's 阮祖亮's slides, so the two companies' numbers can be cross-checked): lab loss has reached 0.04 dB/km, average splice loss is 0.05 dB, and a thousand-kilometer DCI demo showed average loss of 0.12 dB/km.

Bandwidth: Dispersion Is the Real Ceiling

張磊 pointed out a physical limit many overlook: bandwidth is mainly limited by dispersion, and dispersion tolerance is inversely proportional to the square of the data rate.

Single-mode fiber's dispersion curve is about −4 ps/(nm·km) at 1250 nm, crosses zero near 1300 nm, and reaches +20 ps/(nm·km) at 1650 nm. Hollow-core fiber (HCF) is nearly flat across the whole band, between −1 and +1 ps/(nm·km). That means the reach of 200G/400G-per-lane WDM signals in the O-band is no longer bound by dispersion.

The limits are even stricter on the multimode side: at 200 Gb/s per lane, standard OM4 supports only 40 m links, with very demanding requirements on the source's modal bandwidth and spectral width. That explains exactly why Meituan is putting effort into the eSR standard.

Three Paths, Each Mapped to a Layer

YOFC's new fiber solutions come as a clear mapping table:

Problem	Solution	Layer
Switch front-panel density	CPO + fiber plug interface	Scale-up
Inter-building cables too thick	Reduced-diameter fiber (250 → 200 μm, 36% smaller cross-section, ~1.5x more fibers in the same cross-section)	Scale-out / Scale-across
Per-fiber transmission density	Multi-core fiber (MCF), 4–38 optical channels per fiber	Scale-up internal interconnect
DCI cross-campus latency	Hollow-core fiber (−33%, for 10 km–1,000 km)	Scale-across
Intra-cluster latency	Hollow-core (−30% between racks, GPU utilization up 15–25%)	Scale-up / Scale-out
Polarization maintenance inside CPO	PM fiber + G.657 bend-insensitive fiber (7.5 mm minimum bend radius)	Inside the CPO package

Reduced-diameter, multi-core and hollow-core fibers, and which DCN / DCI / scale-across layer each maps to (Source: compiled from YOFC and H3C on-site slides)

Why CPO Is "Pickier" About Fiber

張磊 gave three very specific reasons:

Polarization sensitivity: SiPh waveguides carry only the fundamental TE mode; once polarization drifts, modulation efficiency and link quality degrade immediately, so the path from external light source to SiPh engine must be polarization-maintaining end to end
Dense bending: hundreds of fibers at the package edge must turn on tight radii, where ordinary fiber's bend loss soars, hence G.657 bend-insensitive fiber
Density limits: a 204.8T front panel needs to route out thousands of fibers, and cable diameter and bend radius directly decide whether it fits

DWDM moving down into the DCN is another trend: MRM microring modulators natively support WDM and scale easily (their weakness is high thermal sensitivity); the slide cited Lightmatter's 16-wavelength DWDM optical engine for CPO.

That "Historic Mission"

張磊's final summary was a single sentence, and it was the best closer of the forum:

Optical fiber, traditionally used for long-distance communications, will take on the historic mission of short-reach, high-speed data interconnect in the AI era.

12. Conclusion

First, NPO's "Durability" Is Real, but Not for the Reasons Most People Give

The usual market argument for NPO is "CPO isn't ready yet, so use NPO as a bridge." That framing was corrected three times at this forum.

Meituan says it has gone from stopgap to long-term roadmap; HGGenuine says NPO covers the mainstream, CPO breaks through at the high end, with long-term tiered coexistence; Marvell says it's additive, not a replacement. The most honest was FiberHome's 邱晨: NPO becomes a durable form in China because it solves both a technology problem and a supply chain problem at once. Copper hitting its limit at 224G is the technology reason; domestic PAM4 DSPs being a bottleneck is the industry reason; and NPO is the only answer that satisfies both.

What does this mean? It means China's NPO demand won't disappear as CPO matures, because the industry conditions that make NPO work (open disaggregation, reuse of the existing module supply chain, no lock-in to a single switch ASIC vendor) won't change as CPO yields ramp.

HGGenuine's 2030 shipment mix table is the best footnote: in the 3.2T generation, CPO takes 51% while pluggables plus LPO still hold 49%. Nobody eats anybody.

Second, H3C's Dissent Deserves to Be Taken Seriously, Because It Points to 448G

阮祖亮's line that "NPO saves nothing it should" sounds like contrarianism in the 224G generation, but placed in the 448G context it becomes a sharp warning.

Look at the numbers: the linear loss budget at 224G/lane is only 22 dB, while NPO's measured insertion loss is 7–9 dB, so there is margin. But at 448G the Nyquist frequency doubles to 106.25 GHz, channel loss deteriorates sharply, and the signal degradation from NPO's abrupt interface transitions (socket, connector, package edge) can't be compensated.

In other words, the lifespan of the NPO path depends on when 448G actually needs to deploy. HGGenuine's standards timeline gives the answer: ODCC's 12.8T (448G) UPO definition only starts in 2027 Q3. So NPO has at least the full 2026–2029 window, and HiSilicon's roadmap also places 448G at 2030+.

Within that window, NPO is safe. Once the window closes, H3C is right.

Third, the Real Decider Lies in Two "Unglamorous" Links

Across the forum, the two things that looked least like headlines are the ones that actually decide the outcome.

The first is laser chips. Lumentum gave few numbers, but everything it said is a barrier to entry: EMLs are among the hardest semiconductors to produce, 30 years of accumulated know-how, four InP fabs expanding at once, and a new fab that only starts producing wafers in CY28. HiSilicon spent four full pages on the three challenges of integrated high-power light sources: choosing aluminum quantum wells for high-temperature performance, proving reliability over 10,000 hours, and holding single-mode yield at 80°C / 200 mA.

The moderator's "silicon photonics can't even emit light" was the most clear-eyed line of the forum. No matter how architectures evolve (pluggable, LPO, NPO, CPO, XPO), every path starts with an InP or GaAs laser. And capacity build-out for this link is measured in years.

The second is fiber and connectors. YOFC's table made it plain: AI racks use 10 to 36 times as many fibers as traditional ones, a 10,000-GPU cluster needs 200,000 fibers, and 6,912-fiber cables are becoming standard between campus buildings. CPO's three new requirements for fiber (polarization maintaining, bend-insensitive down to 7.5 mm, reduced diameter to 200 μm) are all materials and process problems, not design problems.

What these two links have in common: neither is on the battlefield of the "architecture war," but whichever architecture wins, they will sell more.

Fourth, Scale-Across Is the Underrated Piece

Three companies at the forum independently pointed to the same thing, yet it gets far less market attention than CPO.

FiberHome's figure puts the Scale Across market at a CAGR above 55%, higher than the 40% for intra-data-center interconnect. Marvell says 3.2T PAM4 only reaches 500 m, so covering 2 km means bringing coherent-lite into the data center. YOFC supplied the physics: cross-data-center training at 40 ms latency inflates iteration time by 9x, and hollow-core fiber can cut latency by 33%.

Strung together, the conclusion is: when a single campus's power and land can't support a 100,000-GPU cluster, "treating multiple data centers as one" is the only path, and its technology stack (coherent moving inward, hollow-core fiber, ultra-low-latency box equipment) is completely different from the one inside the data center.

Fifth, What It Means for Taiwan's Supply Chain

This forum was an internal conversation within China's supply chain: nine of the eleven talks came from Chinese companies or a Chinese-vendor perspective, with Marvell and Lumentum the only two outside voices. But Taiwan's supply chain has a very clear position on this map.

Tier one: the links named directly. When Meituan's slide described the 224G/lane packaging path, it said "CoWoS is in mature volume production, CoPoS is ramping yield"; both terms belong to TSMC. And the advanced packaging, SiPh platforms, testing and optical coupling that NPO and CPO both need are exactly the set of capabilities repeatedly discussed in Taiwan in recent years at the SEMICON Taiwan 2026 SiPh International Forum.

Tier two: links unaffected by the architecture war. FAUs, connectors, optical coupling, PM fiber assemblies and external light source modules (ELSFP) are needed by NPO, CPO and XPO alike. Tencent, FiberHome and HiSilicon all talked about "compression mounting," "fiber routing," "contamination" and "end faces," and that is precisely the home turf of Taiwan's passive optical component makers.

Tier three: the window. HGGenuine's standards table tells us all four NPO standards bodies publish in 2027 H1 and enter volume commercial deployment in 2027 Q2. Tencent's 512-card superpod deployment is slotted for 2027 Q1. FiberHome forecasts volume commercial NPO in 2027. Three independent sources point to the same moment: 2027 is year one of NPO volume production.

That means: the window for spec validation and sample delivery runs from 2026 H2 to 2027 H1. If a Taiwanese supplier doesn't already have NPO-related samples under customer evaluation, it will miss the 2027 wave. And the window for external light sources (ELS/ELSFP) opens even earlier, because they are shared by NPO and CPO, and Tencent's slide explicitly states that "NPO uses external, pluggable ELS."

As for 448G, that's a 2029–2030 story; what's being positioned now is materials (TFLN, InP MZ) and packaging (72 channels, 2D FAUs).

The last word goes to the line on 邵海峰's slide: it's not about how many chips we can stack, but about making those chips work together. All eleven slide decks at this forum were really saying the same thing: make thousands upon thousands of chips behave like one, and the path between them can only be light.