Open CPX 1.0 Teardown: CPO Finally Gets a Standard Socket — Dimensions, Forces and Tolerances Laid Bare
On September 16, 2026, the Open CPX MSA formally approved Specification 1.0. This 78-page document does something CPO has failed to do for a decade: it turns "how an optical engine plugs into the board" from every vendor's proprietary design into a single drawing anyone can tool up against.
Three numbers to remember first:
Type-1 connector: 200 pins (8 rows × 25 positions); Type-2: 300 pins (12 rows × 25 positions). Both must hold insertion loss within -1.05 dB / -0.7 dB at 53.125 GHz.
Mated tolerance x/y ±30 µm, z ±125 µm, yet the capture range is only 0.30 mm / 0.35 mm — the number that decides whether a technician can seat it by hand.
Type-1 module beachfront width MAX 17.0 mm, module pitch MAX 18.0 mm, max power per module 115.65 W. These three numbers tell you how many optical engines fit along each edge of an ASIC.
The real point: Open CPX does not specify what goes inside the optical engine. It only specifies the interface. That means, from today, CPO competition formally shifts away from system-integration capability toward who can build optical engines that are both cheap and reliable.
1. CPO Has Been Stuck for Ten Years — and It Was Never the Optics
The technical logic of CPO (Co-Packaged Optics) has held for a decade: move the optical engine next to the ASIC, cut ten-plus centimeters of PCB trace from the electrical path, halve the power and slash channel loss. Nobody disputes that.
Yet it never took off — not because of the optics, but because nobody dared to be locked in.
Why have pluggable optics (QSFP-DD, OSFP) won for twenty years? Because they have MSAs. Any switch vendor cuts a cage into the faceplate and a dozen module makers worldwide can supply it; when a module dies, a field engineer pulls it and swaps in a new one. The problem with CPO: the optical engine is soldered next to the package substrate — if it fails, the whole board is scrapped, and every vendor's pinout is different.
So system vendors faced a deadlock: adopting CPO meant locking into a single optical-engine supplier; refusing lock-in meant no second source. That is not a technical problem — it is a business-model problem.
Open CPX 1.0 exists to cut that knot. Its approach is clever — don't build soldered-down CPO, build "pluggable CPO": solder a socket onto the package substrate (or the near-package motherboard) and let the optics module plug in via its connector. What gets soldered down is a $20 socket, not an optical engine worth hundreds of dollars.
Lightmatter's Bijan Nowroozi spelled out this path at OCP APAC earlier this year, saying the spec would be delivered in Q4 — it has now been delivered, and he is on the spec's voting roster himself. For background, see 2026 OCP APAC Summit | Lightmatter | Bijan Nowroozi | Half the Compute Is Waiting on the Network: CPO Goes from Proprietary to Open, Spec Due in Q4.
This figure hides Open CPX's most underrated move: the same Type-1 RF socket accepts either an optics module or a copper-cable connector. A system vendor can ship with copper first and switch to optics once optical-engine yields improve — no board respin, no new part number. That is insurance for the purchasing department, not for engineers.
2. Two Sockets, Four Modules: Getting the Taxonomy Straight
The spec opens by defining two socket types, which differ in only one thing: whether the RF and Management & Power (MP) pin fields are separated.
Type-1 | Type-2 | |
Socket makeup | RF socket + MP socket (two parts; may sit on different mounting planes) | Combined RF/MP (single part, single board plane) |
Max channels | 32 ch (64 differential lanes) | 36 ch (72 differential lanes) |
Bandwidth | 6.4 Tbps | 7.2 Tbps |
RF pins | 8 rows × 25 positions = 200 | 12 rows × 25 positions = 300 (shared RF+MP) |
Typical scenario | RF socket on the ASIC package substrate, MP socket on the motherboard | Everything on the same PCB (near-package optics) |
Type-1 is designed for true CPO. It lets the high-speed RF socket sit on the ASIC package substrate (shortest electrical path), while the MP socket that delivers power and management signals sits on the motherboard below — the two planes differ by 3±0.5 mm. This "one module mating across two planes" design is the source of all of Type-1's mechanical-tolerance complexity.
Type-2 is designed for NPO (Near-Package Optics). Everything sits on one board: simple, cheap, easy tolerances — at the cost of a slightly longer electrical path.
On the module side, there are ELM (External Laser Module) and ILM (Internal Laser Module), crossing into four variants: Type-1-ELM, Type-2-ELM, Type-1-ILM and Type-2-ILM. The compatibility matrix is simple — Type-1 sockets take only Type-1 modules, Type-2 sockets take only Type-2 modules, while ELM/ILM are interchangeable.
Module labels are fixed too: CPX-T1E-{Nch}-{xxx} (Type-1-ELM), CPX-T2I-{Nch}-{xxx} (Type-2-ILM) and so on, with {Nch} stating the channel count directly (16, 18, 32, 36). Depopulated modules are legal, as long as channels are filled sequentially starting from channel 1 of the pin map and declared accurately in CMIS. This rule effectively pre-opens the road for a lower-cost product line.
3. The Type-1 RF Connector: 200 Pins Packed into 16.5 × 14.7 mm
This is the heart of the whole spec and the focus of this article.
Pin layout
The Type-1 RF socket and connector each have 8 rows (Row A–H) × 25 positions (Column 1–25) = 200 contacts. The layout logic is "differential pairs with grounds between them": a row runs G / p / n / G / p / n / ... / G, so 25 positions divide neatly into 8 differential pairs + 9 grounds. The spec also allows vendors to insert extra ground contacts between rows for impedance return paths and crosstalk isolation.
Do the math: 8 rows × 8 pairs = 64 differential lanes (32 TX + 32 RX), exactly 32 channels. The allocation is split symmetrically top and bottom — Rows A–D are all RX (module output to host), Rows E–H are all TX (host input to module). This "TX and RX in separate rows" arrangement is itself a crosstalk design: the noisiest TX and the most sensitive RX are separated by four full rows of ground and distance.
Pad dimensions
Contact pad diameter Ø0.25 mm — the smallest mechanical feature in the entire spec.
Row pitch (y direction) 1.50 mm, three equal segments.
Column pitch (x direction) is non-uniform: a repeating 1.83 / 1.77 / 1.83 / 0.89 mm cycle — not a mistake, but a way to keep the two pins of each differential pair close (strong coupling) while pushing pairs apart (weak crosstalk).
The socket side also has solder legs for self-alignment and retention structures; Detail B shows dimensions in 1.90 / 2.10 / 3.20 mm steps, with heights of 1.20 / 2.20 mm.
Outline and keep-out
These are the numbers layout engineers actually need:
Item | Socket side (soldered to motherboard/substrate) | Connector side (soldered to module substrate) |
RF outline | 16.50 × 14.70 mm | 18.20 × 14.60 mm |
MP outline | 6.60 × 13.40 mm (inner 11.4) | 10.50 × 15.60 mm (inner 14.00) |
Total RF + MP span | 28.63 mm | 31.55 mm |
RF center to MP center | Dimensioned in segments: 7.65 + 8.65 + 8.65 | 9.25 + 9.25 (RF half-width) + 7.05 |
Datum | RF pin-field center + three circular fiducials (Ø0.5 / Ø0.25) | Same, and must be visible on the underside of the finished module |
Note that the connector side is larger than the socket side (31.55 vs 28.63 mm). That is normal for mating connectors — the male housing wraps around the female. When designing the module substrate, use the connector-side numbers for keep-out.
The rule on the three fiducials is worth noting: the spec says their drawn positions are only an "informative example" and vendors may choose their own, but they must uniquely determine the RF pin-field center and must be clearly visible on the underside of the assembled module. This gives pick-and-place and AOI something to register against — misalign a socket by 100 µm and a 53 GHz channel starts losing margin.
High-frequency performance: -1.05 dB is a hard limit
Parameter (≤53.125 GHz, 92.5 Ω) | Type-1 limit |
Insertion Loss | -1.05 dB |
Return Loss | -15 dB |
Near-end crosstalk (NEXT) | -60 dB |
Far-end crosstalk (FEXT) | -40 dB |
53.125 GHz is the Nyquist frequency of 106.25 GBd PAM4 (212.5 Gbps/lane). One connector eating 1.05 dB doesn't sound like much, but the entire in-module channel budget is only 3 dB (broken down in Section 7) — this one part consumes a third of it.
It also explains why impedance is set at 92.5 Ω differential rather than the industry-standard 100 Ω — in a dense, metal-shielded contact array, 92.5 Ω is the compromise that satisfies both density and impedance. The entire spec, from connector to TX/RX terminations to host-side terminations, is unified at 92.5 Ω.
Tolerances: where the devil lives
These numbers decide whether this interface can be assembled by real people:
Mated Error | Value |
x direction | ±30 µm |
y direction | ±30 µm |
z direction (stack height) | ±125 µm |
Capture Range | Value |
--- | --- |
x direction | 0.30 mm |
y direction | 0.35 mm |
Rotation about x | 3.0° |
Rotation about y | 2.0° |
Rotation about z | 0.40° |
Read these two sets of numbers separately. "Capture range" is how far off you can be before insertion; "mated error" is how much offset remains after insertion. A 0.30 mm capture range paired with ±30 µm final accuracy means the connector must use its own chamfers and guide posts to absorb ten times the initial error — the spec calls this "self-alignment" and "self-centering" and explicitly requires: coarse alignment → fine alignment completed before contacts touch → moderate misalignment must not damage contacts → repeatable mating.
Forces: 60 N insertion, 300 N ceiling
Item | Spec |
RF insertion force | ≤ 60 N |
RF extraction force | ≤ 35 N |
Recommended retention force (system use) | ≥ 30 N |
Max force in z | ≤ 300 N |
Sustained mated pull tolerance (x) | ≥ 11 N |
Sustained mated pull tolerance (y) | ≥ 25 N |
The single most important sentence: "No external retention forces shall be needed" to keep the socket and connector mated. This is completely different from pluggable optics — OSFP relies on a cage and latch, while Open CPX relies on the connector's own friction. The recommended 30 N retention force is insurance for system vendors, not a requirement.
The 300 N z-direction ceiling is a red line for thermal design: the clamping force of a cold plate pressing on the module lid must not exceed it.
Soldering is specified as low-temperature or lead-free solder, and additional epoxy or solder reinforcement is allowed to keep solder joints from being torn apart by thermal stress in operation.
4. The MP Connector: 14 Pins Must Deliver 115 W — and Absorb 0.5 mm of Error
Type-1's second connector — MP (Management & Power) — is the most elegant design in the entire spec.
Pin definition: 14 pins, two rows
Pin | Signal | Description |
X1 / X7 | GND | Max 5 A each |
Y1 / Y7 | Vdc (+12 V) | Max 5 A each; ≤ 9.5 A total per module |
Y4 | Vcc (+3.3 V) | Max 0.5 A, for the in-module microcontroller |
X6 / Y6 | CMIS_SCL / CMIS_SDA | Primary management interface (I²C, LVCMOS I/O, open drain + host-side pull-up) |
X2 / Y2 | ELS_SCL / ELS_SDA | Second TWI for the external laser source |
X3 / Y3 | ELS_PrsL / ELS_IntL | External laser present / interrupt |
X4 | ResetL | CPX and ELS reset |
X5 | ModPrsL/LPModeL | Three-level logic (presence detect + low-power mode combined on one pin) |
Y5 | IntL | CPX interrupt output |
Two Vdc pins × 5 A plus one Vcc pin × 0.5 A gives, at nominal voltage, a maximum of 115.65 W per Type-1 module.
The X5 ModPrsL/LPModeL three-level pin is a pin-saving trick: using three voltage bands, it squeezes "is the module present" and "should it enter low-power mode" into a single pin. With a budget of only 14 pins, this isn't showing off — it's necessary.
Forces: 5 N, 12× lower than RF
Item | Spec |
MP insertion force | ≤ 5 N |
MP extraction force | ≥ 0.5 N and ≤ insertion force |
Type-1 CPX total insertion force (RF + MP) | ≤ 65 N |
Type-1 CPX total extraction force | ≤ 36 N |
60 N (RF) + 5 N (MP) = 65 N — the numbers add up exactly. The MP connector is deliberately made very soft, because it must not compete with the RF connector for positioning control.
Float: the real reason MP exists
Mated error | Value | Max reaction force |
x direction | ±0.6 mm | ≤ 5.3 N |
y direction | ±0.6 mm | ≤ 12.5 N |
z direction | ±0.5 mm | No reaction force, no hard stop |
Tilt about y | ±2° | — |
Tilt about x | ±0.5° | — |
Rotation about z | ±5° | — |
Compared with the RF connector's ±30 µm, MP's ±0.6 mm is twenty times larger. That isn't a lack of precision — it's intentional.
The spec is explicit: "The mated stack height (z) tolerance is set by the RF connector/socket hard stop; the MP connector shall not provide a hard stop." In other words, 100% of positioning authority for the Type-1 interface goes to the RF connector; the MP connector's job is to act as a spring that soaks up all the accumulated error.
Where does the accumulated error come from? The spec gives a concrete example:
On the module substrate, the RF and MP connectors each have a placement error of ±50 µm
So the relative position error between them can reach ±100 µm (in x and y each)
On the host board, the RF socket and MP socket also have a relative error, capped at ±500 µm
Worst case: after RF alignment, the MP connector and MP socket can be off by more than 200 µm, all of which must be absorbed by MP float
The cross-sections show the MP connector uses two terminal cross-sections: narrower signal contacts and wider power contacts (dimensioned at roughly 2.1 mm and 3.7 mm respectively). Each pin carries 5 A, so contact resistance and temperature rise are hard specs and power pins must be enlarged — the price of squeezing 115 W through 14 pins.
Two stack heights
The MP socket comes in two versions: 10 mm and 13 mm stack height.
RF and MP soldered on the same plane (near-package scenario) → use the 10 mm version
MP soldered on a plane 3±0.5 mm lower than RF (true CPO, RF on the package substrate) → use the 13 mm version
The key: the module-side MP connector is always the same part, regardless of which system it plugs into. System vendors absorb the plane difference with sockets of different heights, so module makers stock only one part. This rule directly determines module makers' BOM complexity — a thoughtful piece of spec writing.
5. Type-2: 300 Pins, One Board, -0.7 dB
Type-2 merges RF and MP into a single connector, with straightforward costs and benefits.
Item | Type-2 spec |
Pin array | 12 rows (Row A–L) × 25 positions = 300 contacts |
Socket outline | 32.00 × 15.95 mm |
Connector outline | 32.00 × 15.95 mm (symmetric, 15.75 + 15.75 from center) |
Pad diameter | Ø0.25 mm |
Row pitch | 1.50 mm × 4 segments |
Column pitch | 2.26 / 2.34 / 2.26 / 2.34 / 2.26 / 1.67 mm |
Insertion loss | -0.7 dB (better than Type-1's -1.05 dB) |
Return loss | -15 dB |
NEXT / FEXT | -60 dB / -45 dB (FEXT 5 dB better than Type-1) |
Type-2's high-frequency performance is actually better than Type-1's — 0.35 dB less insertion loss and 5 dB better FEXT. The reason is intuitive: one connector, one plane, no mechanical margin reserved for cross-plane float, so the signal path can be shorter and cleaner.
Tolerances are also far more relaxed:
Item | Type-2 | vs. Type-1 |
Mated error x/y | ±30 µm | Same |
Mated error z | ±125 µm | Same |
Capture range x | 0.8 mm | 0.30 mm |
Capture range y | 0.9 mm | 0.35 mm |
Rotation about x | 8.0° | 3.0° |
Rotation about y | 5.5° | 2.0° |
Rotation about z | 0.5° | 0.40° |
Insertion force | ≤ 55 N | ≤ 60 N (RF) / ≤ 65 N (total) |
Extraction force | ≤ 32 N | ≤ 35 N (RF) / ≤ 36 N (total) |
Recommended retention force | ≥ 30 N | ≥ 30 N |
Max force in z | ≤ 300 N | ≤ 300 N |
Capture range 2.6× larger, rotational tolerance 2.7× larger — Type-2 is clearly the easier one to assemble and service.
The pin allocation is where Type-2's real ingenuity lies. Of the 300 contacts:
All of Row A goes to power: 14 Vdc pins (0.7 A each, 9.8 A total) + 2 Vcc pins (0.7 A each) + ground, for a maximum of 122.22 W at nominal voltage
All of Row B goes to management and reserved pins: CMIS_SCL/SDA, ELS_SCL/SDA, ELS_PrsL, ELS_IntL, ResetL, IntL, ModPrsL/LPModeL, plus three vendor-proprietary pins (PROP1–3, which the host must not connect)
Rows C–G carry RX (36 lanes), Rows H–L carry TX (36 lanes); rows C and H are mixed with reserved pins and carry only 4 pairs each
In other words, what Type-1 solves with two connectors, Type-2 solves by "sacrificing two rows of pins". It trades density for simplicity — and it's a good trade.
One detail worth tracking: the spec specifically notes that the placement of the reserved (RES) pins — 18 in total — is deliberate, so a future revision can support modules up to 155.82 W. Open CPX has already reserved headroom for next-generation power growth — which is almost an admission that "we know 36 channels won't be the end of the road."
6. Module Outline: 17 mm Beachfront and 18 mm Pitch Decide How Many Fit per ASIC Edge
The connector defines "how it plugs in"; the module outline defines "how many fit." These dimensions are the first thing a system architect looks at.
Dimension (mm) | Type-1-ELM | Type-2-ELM | Type-1-ILM | Type-2-ILM |
Module width (x, beachfront) | MAX 17.0 | MAX 17.0 | MAX 22.0 | MAX 22.0 |
Module length (y) | MIN 36.0 / MAX 50.0 | MIN 36.0 / MAX 50.0 | MIN 50.0 / MAX 75.0 | MIN 50.0 / MAX 75.0 |
Module height (z) | MAX 10.0 | MAX 10.0 | MAX 10.0 (first 60 mm) → MAX 13.0 | MAX 10.0 → MAX 13.0 |
Stack height | 10.0 ±0.1 (MP also 13.0 ±0.5) | 7.0 ±0.1 | 10.0 ±0.1 | 7.0 ±0.1 |
Cold-plate contact length | MIN 36.0 | MIN 36.0 | Y_CP = 60.0 | Y_CP = 60.0 |
Fiber exit zone (z) | MAX 10.0 | MAX 10.0 | MAX 13.0 | MAX 13.0 |
Fiber exit zone (x, per side) | MAX 6.5 | MAX 6.5 | MAX 9.5 | MAX 9.5 |
Support feet | 5.0 ±0.1 (at 36.0 ±0.1) | — | 5.0 ±0.1 | 5.0 ±0.1 |
Module pitch MAX 18.0 mm. This is the single most important number. It means the center-to-center distance between two adjacent Type-1 modules is no more than 18 mm, so module width is capped at 17 mm — leaving 1 mm for mechanical and assembly clearance.
Run the numbers: if one edge of an ASIC has 72 mm available, that's 4 modules × 32 channels × 212.5 Gbps = 27.2 Tbps. Fill all four edges and you get the 100 Tbps switch in the spec's Figure 3-1. Open CPX effectively defines the bandwidth-density ceiling for the CPO generation.
ILM is one size larger than ELM (22 mm vs 17 mm wide, 50–75 mm vs 36–50 mm long), because the laser goes inside the module and needs both space and cooling. ILM also adds a stepped profile — "height limited to 10 mm for the first 60 mm, then up to 13 mm" — the cold plate presses only on the first 60 mm, and the raised rear section is left for the laser and driver circuitry.
The module lid is also nailed down: nickel-plated copper, flatness within 0.075 mm, surface roughness within Ra 0.8 µm, and covering 90% of the area (the remaining 10% may hold clips or screws, but nothing may protrude above the lid surface). This is the prerequisite for pressing a liquid cold plate directly onto it.
The thermal conditions themselves are set as follows:
Effective heat-transfer coefficient of cold plate + thermal interface material (TIM) ≥ 11,000 W/m²·K (effective thermal resistance ≤ 0.91 K·cm²/W)
Coolant inlet temperature 52 °C
Host substrate temperature 85 °C
These conditions apply to modules of 40 W or less; higher power requires a stronger cold plate
A 52 °C inlet is typical of warm-water liquid cooling in data centers, and an 85 °C substrate is the real environment next to an ASIC. Put the two numbers together and the message is clear: CPO modules must work while being baked by the ASIC with only warm water available.
As for fiber, the spec does not mandate a connector type — only the fiber exit zone and strain relief:
Test | Requirement | Reference |
Cable retention | 0.5 kg / 1 minute | GR-468-CORE 3.3.1.3.3 |
Side pull | 0.25 kg, 90°, 22–28 cm from housing | GR-468-CORE 3.3.1.3.2 |
Twist | 0.5 kg, 10 cycles, 3 cm from housing | GR-468-CORE 3.3.1.3.1 |
Straight pull | 2.2 N per fiber bundle | GR-1435-CORE 4.6.2.6.4 |
The signal-side connector is left to the application; the spec lists MPO-12/16, MMC-12/16/24, SN-MT-12/16/24 and MXC-16, and recommends a male connector on the module side, so the same female patch cords used for other pluggable form factors can plug straight in. We broke down the yield problem of detachable fiber interfaces in 2026 OCP APAC Summit | SENKO | Chengting Chen | Detachable Fiber Interfaces: Whether CPO Can Scale Hinges on That 0.15 dB.
The external-laser fiber counts for ELM are tabulated directly:
Channels | 16 | 18 | 32 | 36 |
ELS fiber count | ≤ 4 | ≤ 6 | ≤ 8 | ≤ 12 |
Split ratio (per laser fiber to TX lanes) | 1 → ≥4 | 1 → ≥3 | 1 → ≥4 | 1 → ≥3 |
One laser fiber feeding 3–4 TX lanes means the per-port output power and splitting loss of the external laser source are the hidden bottleneck of ELM designs.
7. Electrical Budget: 15 dB Outside, 3 dB Inside
Open CPX doesn't invent its own high-speed electrical spec; it references OIF CEI-224G-LINEAR-PAM4, OIF 224G-RTLR and IEEE 802.3dj C2M. But it makes one key deviation:
Electrical channel Nyquist loss is reduced from 22 dB to 18 dB (Die-to-Die), corresponding to a 15 dB (Die-to-Socket) electrical loss budget from the SerDes bump to below the CPX socket.
This 15 dB applies globally — CPO or NPO, the host-side budget is 15 dB. Meanwhile, total in-module channel loss is held within 3 dB, with the "mated connector + socket" taking < 1 dB and "connector to module chip" taking < 2 dB.
Put this figure next to the -1.05 dB from Section 3 and something stands out: the Type-1 connector's -1.05 dB spec already exceeds the in-module "connector + socket < 1 dB" allocation. It's not a contradiction — the former is a single-point limit at 53.125 GHz, the latter an equivalent channel budget, measured differently. But it tells module designers plainly: the connector nearly uses up the inside budget, leaving 2 dB for the entire path from substrate to optical-engine chip.
A few other numbers engineers will use directly:
92.5 Ω differential impedance end to end (TX input, RX output and host-side termination all consistent)
Single-ended voltage range [-50 mV, +960 mV] (common-mode voltage varies with differential swing; the spec includes a full range chart)
TX squelch threshold 50 mV (differential peak-to-peak, hit ratio 1×10⁻⁴), same for 112G and 224G
RX squelch enabled by default, can be disabled via TWI
Modules may or may not be AC-coupled; if not, they must tolerate the common-mode voltage range themselves
Power and management:
Item | Spec |
Vdc | 12 V, range 10.8–13.2 V (including ripple and droop) |
Vcc | 3.3 V, range 3.135–3.465 V |
Power modes | Two levels, low-power / high-power; modules always declare Power Class 8 |
Low-power mode | ≤ 5 W (3.3 V only); Type-1 Icc ≤ 0.5 A, Type-2 ≤ 1.4 A |
Power Class 8 limit | P_8 ≤ 134.2 W (130 W on 12 V, 5 W on 3.3 V) |
Steady-state current limit | Type-1 9.5 A, Type-2 9.8 A (12 V) |
Inrush timing | T_ip ≤ 50 µs、T_init ≤ 500 ms、T_hplp ≤ 200 µs |
Voltage slew tolerance | 175 mV/ms; no dropped packets or TWI errors allowed during it |
Management interface | CMIS 5.3, I²C address A0h, ModSel not supported |
Noise | Host ≤ 25 mV RMS on Vcc, ≤ 90 mV RMS on Vdc; module PSNR tolerance 240 mV p-p |
Two points worth noting:
First, the Power Class 8 limit of 134.2 W is higher than what the pins can actually deliver: 115.65 W (Type-1) and 122.22 W (Type-2). This gap means the real ceiling for high-power modules will be set by pin current, not by power class — which is exactly why Type-2 reserves 18 RES pins pointing toward 155.82 W.
Second, ModSel is not supported. The host must run point-to-point I²C to every module or add an I²C switch. Sixteen modules along an ASIC edge means 16 independent I²C buses or a full switch tree — a hidden cost for system vendors, and the reason the spec already signals a move toward I3C.
8. Who's at the Table — and What This Really Means
The Promoter list has only six companies: Ciena, Coherent, Marvell, Molex, Samtec and Terahop. The editor is Peter Winzer of Ciena, the chair is Ian Alderdice of Ciena, and the co-chairs come from Coherent and Terahop.
The lineup itself is the message: two connector giants (Molex, Samtec) + two optical-component giants (Coherent, Ciena) + one ASIC/SerDes giant (Marvell). Connector makers at the Promoter level show that this spec was written from day one for "tooling and volume production," not as an academic roadmap.
The voting roster is much longer, spanning:
Systems / cloud: Dell, HPE, Ruijie, Alpha Networks
Silicon / SerDes: Intel, Qualcomm, Credo, Semtech, Astera Labs, Marvell
Optical components / modules: Applied Optoelectronics, Lumentum, Source Photonics, O-Net, ColorChip, Enablence, Accton, TFC
Connectors / mechanics: Amphenol, TE Connectivity, LOTES, Foxconn Interconnect, Hakusan
CPO startups: Lightmatter, Avicena, Lyntera, Nexthop, PhotonicX AI, Upscale AI
Test: Multilane, Viavi, Wilder Technologies
Having test vendors on the list is the most pragmatic aspect of this spec. With Multilane, Viavi and Wilder involved, compliance test fixtures will follow — exactly what let the pluggable-optics ecosystem snowball back in the day. CPO used to be stuck because "nobody could independently verify someone else's optical engine"; that link now has an owner.
Taiwan's supply-chain position is also clear: Accton, Alpha Networks, Foxconn Interconnect, LOTES and AOI's Taiwan fab are all on the list. LOTES and Foxconn, on the connector side, are the most direct beneficiaries of this spec — once the interface is standardized, orders shift from "design wins" to "part numbers."
Conclusion
The real value of Open CPX 1.0 isn't that it defines 6.4 Tbps or 7.2 Tbps — it's that it turns the hardest part of CPO — the mechanical interface — into a public good.
Doing CPO used to mean the system vendor and the optical-engine maker co-developing from mechanical design onward, one design tied to one customer. Now the socket outline is 16.50 × 14.70 mm, contacts are Ø0.25 mm at 1.50 mm pitch, insertion force 60 N, tolerance ±30 µm, stack height 10 mm or 13 mm — these numbers are written down, and anyone can build to them.
Three things are worth tracking:
Tooling timelines. Molex and Samtec sit at the Promoter level, and STEP and DXF files have been released with the spec. When the first compliant socket samples ship is the first checkpoint for Open CPX going from paper to supply chain.
Whether Type-1 or Type-2 takes off first. On tolerances, Type-2 is far easier to assemble (2.6× the capture range) and even performs better at high frequency (-0.7 dB vs -1.05 dB). Type-1 for true CPO is technically more enticing, but NPO-oriented Type-2 is more likely to reach volume first. Open CPX doesn't pick a side in the CPO vs NPO route battle — it defines both — and the market usually picks the one that's easier to build first.
Those 18 reserved pins. Type-2 reserves headroom to 155.82 W, meaning the MSA is already looking at the next generation. When 212.5 Gbps/lane moves to 425 Gbps/lane, will the spec keep the same mechanical dimensions? If so, the molds cut today are a ten-year business; if not, every investment made now must be recalculated.
CPO has cried wolf too many times over the past decade. What's different this time: whether the wolf arrives no longer matters — what matters is that someone has finally drawn the dimensions of the fence.
References
Open CPX MSA, Specification for Co-packaged and Near-Package Connector and Optics Module, Rev 1.0, 2026 September 16. Editor: Peter Winzer (Ciena). Source: OpenCPXMSA.org
OIF Common Management Interface Specification (CMIS) 5.3
OIF CEI-224G-LINEAR-PAM4 (in development, draft OIF2024.522.05)
IEEE Std 802.3dj Annex 176D / Clause 180
Telcordia GR-468-CORE Issue 2 / GR-1435-CORE Issue 3
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