ECTC 2026 | Mitsubishi Electric | High-Density Integration of III-V Devices and EICs using Vertical-Coupled Photonic Packages with Glass-IP and Redistribution Layers

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At ECTC 2026, Mitsubishi Electric presented a CPO/NPO packaging architecture that departs from the silicon photonics mainstream: a glass interposer (Glass-IP) with redistribution layers (RDL), with III-V electro-absorption modulated lasers (EMLs) and photodetectors flip-chip bonded onto the glass, the driver/TIA (EIC) integrated on the backside, and TGVs shortening the electrical path. Why EMLs instead of silicon photonics modulators? Because inter-GPU links are approaching 400 Gbps per lane, conventional modulator assemblies struggle to keep up, and III-V EMLs already reach 100+ Gbaud. The glass interposer also doubles as a thermal barrier against the ASIC. Prototype results: 89 GHz electrical 3-dB bandwidth, 106.25 Gbaud PAM4 back-to-back, and 2.37 dB TDECQ; for vertical coupling, a microprism plus microlens array forms a detachable FAU connector needing only a single active alignment, with simulated insertion loss below 1 dB. In one sentence: as each lane races toward 400 Gbps, Mitsubishi is betting on the high-speed path of “glass interposer + flip-chipped III-V EML + backside EIC.”

1. Background: Not Silicon Photonics Modulators, but III-V EMLs Flip-Chipped on Glass

This paper from Mitsubishi Electric (Japan) was presented at the 2026 IEEE 76th ECTC. LLM-driven AI systems keep pushing per-I/O data rates higher to feed GPU bandwidth, driving demand for high edge density (Tbps/mm) and low power in OOI and NPO. Inter-GPU links have reached 200 Gbps per lane and are approaching 400 Gbps—a challenge for many conventional modulator assemblies—while Mitsubishi has previously demonstrated 100+ Gbaud with III-V EMLs.

Their proposal: use a glass interposer (Glass-IP: high rigidity, low CTE, low dielectric constant) plus RDL, flip-chip bond EMLs/PDs onto the glass, integrate the EIC on the backside, and use TGVs to shorten the electrical path for low-power, ultra-high-speed operation. For the advanced packaging platform battle, see The Great Shift in Optical Packaging (Part 3): TSMC vs ASE vs Intel; for the value of glass as a substrate, see Why the TGV Race Arrives All at Once in 2026.

Fig. 1: Concept of the vertically coupled photonic package with Glass-IP + RDL—EML/PD flip-chipped on glass, EIC integrated on the backside. Mitsubishi Electric, ECTC 2026 - Fig. 1

2. The Core Question: The Whole Paper in One Sentence

What this paper sets out to verify: can a vertically coupled package that uses Glass-IP + RDL to flip-chip III-V EMLs and integrate the EIC on the backside simultaneously deliver ultra-high speed (toward 400 Gbps/lane), low power, detachable optical I/O, and thermal isolation from the ASIC?

The answer is preliminarily yes—89 GHz bandwidth, 106.25 Gbaud PAM4, 2.37 dB TDECQ, plus detachable vertical coupling with simulated loss below 1 dB.

3. Key Figures, One by One

3.1 This Figure Shows How the Glass Interposer Manages Electrical, Optical, and Thermal Paths at Once

This figure (Fig. 1) shows the architecture. The EML (Tx) and surface-illuminated PD (Rx) are flip-chipped onto the Glass-IP, while the driver/TIA EIC is integrated on the backside and connected through TGVs, minimizing the electrical traces between the optical devices and the EIC. Heat is pulled upward through a heat spreader and heat-transfer block (HTB); meanwhile, glass's low thermal conductivity conveniently isolates the optical devices and EIC from the ASIC heat source on the package substrate. A single piece of glass handles electrical (short traces/low parasitics), optical (waveguides/coupling), and thermal (ASIC isolation) duties.

3.2 This Figure Shows That the Detachable Optical Connector Needs Only One Active Alignment

These figures (Fig. 2, Figs. 3–4) cover vertical coupling and the detachable connector. Flip-chipping the EML puts its emission point close to the glass surface, so the bump height h must be raised and the prism distance d chosen correctly to avoid beam clipping. Gaussian beam analysis: with a 1.5 µm spot, h = 20 µm yields almost zero clipping with wide tolerance on d; with a 0.7 µm spot, the design is sensitive to d. The vertical beam passes through a microprism plus microlens array forming a detachable FAU connector, which mates with its receptacle through matching grooves and ridges, so the entire detachable system needs only a single system-level active alignment; simulated lens-to-fiber lateral tolerance is ±0.77 µm (insertion loss ≤1 dB).

Fig. 2: Detachable connector configuration achievable with a single active alignment (microprism + microlens array + receptacle groove mating). Source: Mitsubishi Electric, ECTC 2026 - Fig. 2

3.3 This Figure Shows the Prototype Really Runs at 106 Gbaud

These figures (Figs. 7–9) cover high-frequency measurements. The EML combines a DFB-LD, an electro-absorption modulator (EAM), and a spot-size converter, with electrodes on the chip surface for flip-chip bonding; the RF line runs straight across the package substrate and through a TGV to the EAM, keeping the path short. Measured small-signal 3-dB electrical bandwidth was 89 GHz; driving 106.25 Gbaud PAM4 SSPRQ from a 256 GSa/s AWG with a 15-tap FFE yielded back-to-back TDECQ of 2.37 dB and ER of 4.30 dB. Although the prototype is single-channel, the straight, bend-free RF routing allows narrow-pitch EML integration; extending it to an array can raise aggregate capacity while maintaining high edge density.

4. Technical Highlights

The first highlight is flip-chipping III-V EMLs onto a glass interposer with backside EIC integration—a bet on the “toward 400 Gbps per lane” high-speed path. EMLs already reach 100+ Gbaud, and paired with the short electrical path and low parasitics of glass TGVs, the prototype already hits 89 GHz/106 Gbaud—a high-speed option outside the silicon photonics modulator route.

The second highlight is glass as a combined electrical–optical–thermal platform plus a single-alignment detachable connector. Glass's low thermal conductivity isolates the optical devices and EIC from the ASIC heat source; vertical coupling through microprisms/microlenses forms a detachable FAU that needs just one active alignment, with simulated insertion loss below 1 dB—solving “detachable” and “manufacturable alignment” together.

5. Industry Connection: How Far from Volume Production? Who Benefits?

Distance: this is at the “concept + single-channel prototype” stage—the Tx-side single-channel EML high-speed data looks great, but Rx integration and the full detachable optical I/O package are still presented through simulation and concepts, and arraying plus impedance/layout optimization remain ahead. Mitsubishi states its goals as >100 GHz response and higher per-lane rates in the future.

Beneficiaries: most directly, the III-V/EML and glass interposer ecosystem (Mitsubishi is a major III-V device maker); next, high-edge-density packaging for OOI/NPO that needs 400 Gbps per lane. A sober note: III-V flip-chip on glass is a different bet from the silicon photonics mainstream—its strengths are single-channel speed and EML maturity, while the challenge is whether arraying, yield, and cost can compete with the CMOS volume scale of silicon photonics.

6. Conclusion

The one sentence to remember from this paper: as each lane races toward 400 Gbps, Mitsubishi is betting on the high-speed path of “glass interposer + flip-chipped III-V EML + backside EIC”—and the prototype already delivers 89 GHz, 106.25 Gbaud PAM4, and 2.37 dB TDECQ. For anyone tracking the CPO/NPO route battle, the thing to watch is whether, outside the silicon photonics mainstream, III-V EML flip-chip on glass can ride its single-channel speed and EML maturity past the hurdles of arraying and cost.

References

Kei Masuyama, Mizuki Shirao, Shinji Araki, Kiyotomo Hasegawa, Shinya Okuda, Seiu Higashide, Nobuo Ohata, "High-Density Integration of III-V Devices and EICs using Vertical-Coupled Photonic Packages with Glass-IP and Redistribution Layers," 2026 IEEE 76th ECTC. Mitsubishi Electric Corporation, Japan.