Keio University's "Mosquito method" draws light paths into polymer with a single needle, using a graded-index core to avoid interface scattering for near-material-limit loss — and uses fluid dynamics to beat the needle-size limit for 20 µm pitch. What is the open question for the polymer waveguide route?

CPO volume production is held back by micro-lens pick-and-place and active alignment. AIST turns the lens-mirror into an opto-chiplet embedded during molding, routes light with an Optical RDL, and widens alignment tolerance to ±12 µm.

AIST × KYOCERA have lit up the long-shelved AOP concept for the first time: an embedded SiPh chip, polymer ORDL and 3D micro-mirrors deliver 112 Gbps PAM4 with 3.35 dB TDECQ, passing IEEE specs. How far has the polymer optical-redistribution route come?

imec pushed 3D-stacking hybrid bonding to a 200 nm pitch, but the real message is that the deciding factor has moved from bonding to overlay, CMP and pad design. Why is 200 nm a yield cliff, why are overlay accuracy and electrical yield locked in a linear relationship, and where is the next bottleneck for AI 3D integration?

Qnity builds optical waveguides into the PCB process with BCB dry film: the lowest adoption barrier, 0.07–0.11 dB/cm loss, and it survives reflow and high temperature/high humidity. It also honestly debunks the common assumption that widely spaced multimode waveguides don't crosstalk. Where is the sweet spot for board-level optical interconnect?

CoW hybrid bonding yield is first gated by the initial bonding-front angle. By tuning the angle to D so the bonding wave advances in order from center to edge, ASE lifted yield on 8×12×0.05mm dies from 2.8% to 99%, and held 95–99% on ultra-thin dies with 102.4µm warpage, 6µm pitch and organic interfaces, greatly widening the process window.

600mm panels give FOPLP high utilization but warp easily during assembly. ASE's hybrid flow — RDL on 600mm panels, assembly on 300mm panels — delivers 7.1x productivity at low risk, with 3-layer 5/8µm RDL, ±5µm placement accuracy and passing 3x/6x reflow. A pragmatic panel route for AI packaging.

DNP brought polymer waveguides on glass down to a 10 µm pitch, but the real point is an iron rule: density is paid for with index contrast. Only Δ=2.3% pushes 10 µm crosstalk down to −32.3 dB. Which three material parameters decide whether polymer waveguides can compete?

For glass to work as an advanced packaging interposer, the first hurdle is filling deep, straight TGVs with good copper. Tohoku University combines an electroless nickel seed, chemically tailored electroplating and HIP annealing to fill straight vias in 1 mm-thick glass void-free and grow >45 µm grains — a foundational breakthrough for glass TGVs.

W2W Cu-Cu hybrid bonding pushed to 450 nm pitch for the first time while holding high yield (98%/100% across 20 million interconnects). Applied Materials traced the yield killer to residual BTA carbon at the bond interface and engineered the interface chemistry, barrier and anneal — groundwork for 3D DRAM and HBM.

Outside the silicon photonics mainstream, Mitsubishi Electric bets on III-V EMLs flip-chipped onto a glass interposer: the prototype already reaches 89 GHz, 106.25 Gbaud PAM4, and 2.37 dB TDECQ. As each lane heads toward 400 Gbps, can this high-speed path clear the hurdles of arraying and cost?

Sumitomo Electric expands the beam to 32 µm with collimation mirrors, taming two optical-coupling killers at once: a 3 µm misalignment costs only 0.2 dB, and displacement from 25 to 80°C stays under 0.34 µm. Why is beam expansion the key to flip-chip coupling of PICs onto glass waveguide substrates?

Intel's ECTC 2026 paper swaps the flexible fiber array in a detachable CPO connector for a rigid glass coupler. The point is not lower loss but turning fiber alignment from on-site craft into a process-locked, manufacturable, traceable step.

KYOCERA breaks low-loss coupling for CPO modules into three parts: face-down cooling, a curved mirror and a wide-tolerance core. Coupling loss halved to 1.22 dB, ±5 µm tolerance, error-free from 0 to 70°C. Why can't you judge a coupling module by a single loss number?

Silicon modulators hit an RC bottleneck at 50–60 GHz. Nokia Bell Labs flip-chip integrated a TFLN modulator with a commercial driver IC to build the first CPO transmitter of its kind: Vπ·L 2.3 V·cm, EO bandwidth >45 GHz. Coupling loss and heat are the next hurdles.

VCSELs have long been dismissed as 100-meter light sources. Furukawa's 1060nm single-mode VCSEL CPO reaches 2 km at 4.1 pJ/bit using a standard MT ferrule and off-the-shelf fiber. The real breakthrough is not lower power, but finally plugging into existing fiber infrastructure.

On the surface, Corning's ECTC 2026 paper is about lower-loss glass waveguides, but the real moat is the material: an ultra-low-diffusion glass screened from more than 200 formulations that others can't easily copy. Why is thermal reliability the hidden barrier to CPO volume production, and how can glass substrates challenge silicon interposers head-on?

Detachable CPO optical connectors have never managed low loss, passive alignment, high-power handling and detachability all at once. At ECTC 2026, GlobalFoundries and Corning did it for the first time: <1.5 dB/facet, 280 mW, fully passive alignment — a one-two punch of foundry silicon photonics and glass connectors.