ECTC 2026 | ASE | A Novel 600mm Panel Interposer with 300mm Panel Assembly Approach for Advanced Packaging Solution in HPC and AI Applications

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AI/HPC needs ever-larger fan-out areas, but traditional advanced packaging is done almost entirely on 300mm wafers, which limits area utilization. Fan-out panel-level packaging (FOPLP) uses large square panels for higher utilization and throughput — but running RDL, assembly and C4 on a 600mm panel invites warpage and die shift, making yield hard to hold. At ECTC 2026, ASE offered a clever compromise: build the RDL on a 600mm panel, laser-cut it into four 300mm panels, then do flip-chip bonding (FCB), underfill, molding, ball mounting, grinding and singulation on 300mm. This captures both the high RDL utilization of 600mm and the low risk of 300mm assembly. The team built a test vehicle with 2 chiplets plus 3-layer RDL (5/8µm line/space), achieving ±5µm placement accuracy and TTV <10µm, and passing T0 plus 3x/6x reflow stress tests. Estimated productivity: 600mm interposer + 300mm assembly = 7.1x that of wafer. In one line: splitting it into "large panel for RDL, small panel for assembly" is a pragmatic FOPLP route that balances utilization and yield.

1. Background: The Tug-of-War Between Utilization and Yield in Panel-Level Packaging

This paper comes from ASE (Kaohsiung, Taiwan) and was presented at the 2026 IEEE 76th ECTC. AI/HPC integrates multiple Si chiplets + ASICs + HBM with high-density interconnect, so fan-out sizes keep growing. Traditional advanced packaging is mostly done on 300mm wafers, but panels are square, offer higher area utilization, scale better and give more cost flexibility — so the industry is moving toward FOPLP, even up to 600mm×600mm panels.

The problem: maintaining high yield and structural integrity on a 600mm panel through complex RDL and molding is hard — large panels warp easily and dies shift, requiring advanced assembly process control. For the big picture of advanced packaging, see CPO Is Won in Packaging, Not Optics — John Lau on PIC/EIC Heterogeneous Integration; for substrate trade-offs, see Glass Substrates Are No Longer Slideware: Why the TGV Race Came Together in 2026.

Fig. 1: Test vehicle flow — RDL on a 600mm panel → laser-cut into four 300mm panels → flip-chip assembly on 300mm. Source: ASE, ECTC 2026 - Fig. 1

2. The Core Question: The Whole Paper in One Sentence

What this paper sets out to prove: can a hybrid flow — RDL on a 600mm panel, assembly on a 300mm panel — capture both the high utilization of large panels and the low risk of small-panel assembly, and pass reliability?

The answer is yes — it passes T0 and 3x/6x reflow stress tests.

3. Key Figures, One by One

3.1 This figure shows the hybrid flow: "600mm RDL → laser-cut to 300mm → 300mm assembly"

This set of images (Fig. 1) is the core flow. Multi-layer RDL and passivation are first built on a 600mm×600mm panel carrier to complete the fan-out structure; then a laser cuts the 600mm interposer into four 300mm panels; next, 2 SoC dies are flip-chip bonded (FCB) on the 300mm fan-out panel, followed by underfill and mold protection, then backside processing, carrier debonding, ball mounting, mold grinding to expose the top dies, and finally singulation. Why split it this way? Analysis showed that running 600mm end to end is high-risk at the assembly and C4 stages (material queue time, hard-to-control warpage), while "600mm interposer + 300mm assembly" is the optimal solution from a process standpoint.

Key point: splitting into "large panel for RDL, small panel for assembly" is the key to balancing utilization and yield.

3.2 This figure shows "slit coating solves uneven coating on large panels"

This part (Table II, 3-layer 5/8µm RDL) covers the RDL process. On a 600mm panel, conventional spin coating wastes a lot of material, causes uneven flow at the panel edges and pooling at the corners. ASE switched to slit coating, which deposits linearly from one side of the panel to the other with uniform thickness. The result: 3-layer RDL with 5/8µm line/space.

Table IV: Productivity comparison across form factors — 600mm interposer + 300mm assembly = 7.1x wafer, at low risk. Source: ASE, ECTC 2026 - Table IV

3.3 This figure shows "7.1x productivity, ±5µm assembly accuracy, reliability passed"

This set (Table XI, Fig. 5) shows the results. Productivity comparison: 300mm wafer only = 1.0x; 600mm interposer + 600mm assembly + 600mm C4 = 8.0x, but with high assembly/C4 risk; 600mm interposer + 300mm assembly + 300mm C4 = 7.1x at low risk — the best compromise. 300mm assembly accuracy is ±5µm, top-side grinding TTV <10µm, and laser-cut sidewalls are smooth with no micro-cracks. Reliability: passed T0 and 3x and 6x reflow (MR3x, MR6x); cross-sections show no anomalies in top-die solder joints, RDL or ball connections.

4. Technical Highlights

The first highlight is the hybrid "large panel for RDL, small panel for assembly" flow: RDL on a 600mm panel (high utilization), laser-cut into four 300mm panels for assembly (low risk), achieving 7.1x productivity while avoiding the warpage and material risks of full-600mm assembly/C4.

The second highlight is a fully validated process: slit coating solves uneven coating on large panels, delivering 3-layer 5/8µm RDL, ±5µm assembly accuracy and TTV <10µm, and passing T0 plus 3x/6x reflow stress tests — not just a demo, but a test vehicle with reliability data.

5. Industry Link: How Far From Volume Production? Who Benefits?

Distance: maturity sits at "test vehicle + reliability validation" — a TV with 2 chiplets + 3-layer RDL that passed T0 and 3x/6x reflow — but the paper itself acknowledges that panel-level process maturity is still below wafer-level, and large-panel warpage and die shift still need advanced control. It is a process-integration-level step toward volume production.

Beneficiaries: most directly, OSATs and the panel-level supply chain doing large-format fan-out packaging for AI/HPC (this work comes from ASE, the leading OSAT) — AI accelerators need larger fan-out areas, and FOPLP's high utilization hits that need squarely. Next comes the substrate/carrier and panel equipment supply chain. A note of caution: panel-level volume yield, large-panel warpage control and the cost crossover with wafer-level still need time to prove out; the paper's value lies in "using a hybrid panel flow to address FOPLP utilization and yield at once, with reliability data to back it."

6. Conclusion

The one line to remember from this paper: ASE's hybrid flow — RDL on a 600mm panel, assembly on a 300mm panel — captures both large-panel utilization (7.1x productivity) and the low risk of small-panel assembly, delivering 3-layer 5/8µm RDL, ±5µm accuracy and passing 3x/6x reflow. For anyone tracking the AI packaging supply chain, the thing to watch: the challenge of taking FOPLP to 600mm lies in large-panel assembly yield, and ASE's "large-panel RDL + small-panel assembly" split offers a pragmatic answer.

References

Teck Chong Lee, Yungshun Chang, Ping-Feng Yang, Lihong Cao et al., "A Novel 600mm Panel Interposer with 300mm Panel Assembly Approach for Advanced Packaging Solution in HPC and AI Applications," 2026 IEEE 76th ECTC. Advanced Semiconductor Engineering, Inc. (ASE).