ECTC 2026 | AIST × KYOCERA | Demonstration of an Optical Packaged Substrate with Embedded Silicon Photonic Transceiver for High Performance Chiplet Packaging

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At ECTC 2026, AIST and KYOCERA lit up, for the first time, a concept that had sat on the shelf for years — the Active Optical Package (AOP) substrate. They "embedded" a silicon photonic transceiver chip into an organic substrate and used a polymer optical redistribution layer (Optical RDL, ORDL) plus a pair of micro-mirrors to build a 3D vertical optical path between the PIC's silicon waveguides and the polymer waveguides, then pitch-converted and routed the light to optical connectors at the substrate edge. Most importantly, this wasn't a simulation or a passive structure — it actually ran 112 Gbps (56 Gbaud) PAM4 active transmission, with measured TDECQ of 3.35 dB, passing the IEEE 400G / 400G-FR4 threshold of ≤3.4 dB. In one sentence: AOP has moved from slideware to an engineering sample that lights up, modulates and passes signal specs.

1. Background: The Route of "Embedding" Optics into the Substrate

This paper comes from a collaboration between Japan's AIST (National Institute of Advanced Industrial Science and Technology, Tsukuba) and KYOCERA, presented at the 2026 IEEE 76th ECTC. For CPO to break through the bandwidth and energy-efficiency ceiling of electrical interconnect, the hardest step is still coupling between the packaged photonic integrated circuit (PIC) and external fiber. Most CPO today attaches fiber directly to grating couplers, but limited by fiber array pitches of 127 µm and above, optical I/O density can't scale.

AIST's answer isn't a new coupler but a new architecture: embed the entire silicon photonic transceiver chip in an organic substrate, and complete the optical path with a polymer ORDL and a pair of micro-mirrors on the chip — a lower double-taper mirror acts as the PIC's vertical coupler, and an upper 45° mirror bends the light 90° into the polymer waveguide. The ORDL also handles pitch conversion and routes signals to optical connectors at the substrate edge; electrically, an interposer on top connects the driver/TIA/xPU/memory, completing chiplet assembly with conventional electrical packaging and short electrical traces.

We've discussed this "polymer optical redistribution" route in Technical Analysis | Polymer Waveguides Withstand +20 dBm for Six Hours and Building a 1.6T Optical Engine with Fan-Out Packaging: A*STAR's Low-Cost CPO Approach — this AIST paper is the milestone version of the same route, with an embedded chip and active operation.

Fig. 1: Cross-section of the AOP substrate — a silicon photonic transceiver embedded in an organic substrate, with polymer ORDL plus upper and lower micro-mirrors forming a 3D optical path. AIST × KYOCERA, ECTC 2026 - Fig. 1

2. Core Question: The Whole Paper in One Sentence

What the paper sets out to prove: can an AOP architecture — a silicon photonic transceiver embedded in the substrate, with a 3D optical path formed by polymer ORDL and micro-mirrors — actually transmit actively, and does its signal quality meet IEEE specs?

The answer is yes — 112 Gbps PAM4 with 3.35 dB TDECQ, the first active-operation demonstration of AOP.

3. Key Figures, One by One

3.1 This figure shows how light makes a 3D turn inside the substrate

This figure (Fig. 1, Fig. 2) is the backbone of AOP. The process flow is key: trenches are pre-etched in the PIC, the lower double-taper mirror is formed with UV grayscale lithography and coated with reflective metal; the PIC is embedded in a substrate trench (with UV adhesive to match surface height) and planarized with transparent resin; then the polymer waveguide's lower cladding / core / upper cladding are laid down in sequence, and the upper 45° mirror (about 40 µm tall) is formed by UV imprinting. The imprint mold is made on glass by two-photon polymerization (2PP) 3D printing and is reusable — combining 2PP's high precision with imprinting's high throughput.

The key point: the upper mirror is imprinted step-and-repeat, aligned using alignment marks on the chip and mold, so embedding the chip doesn't require ultra-high-precision alignment — the design choice that makes the process manufacturable.

3.2 This figure shows it really lights up and modulates — TDECQ 3.35 dB

This figure (Fig. 4) is the eye diagram of active transmission. CW 1310 nm light from an external laser passes through the ORDL and 3D optical path into the Mach-Zehnder modulator inside the substrate; after modulation it is coupled back through the micro-mirror and ORDL to fiber, and the eye is viewed on a sampling oscilloscope. At 56 Gbaud PAM4 (112 Gbps) with a 64-tap FFE, the eye opens, with measured TDECQ of 3.35 dB, meeting IEEE 400G and 400G-FR4's ≤3.4 dB.

The weight of this number: it isn't a passive loss measurement but proof that the embedded transceiver is actually working with signal quality on spec — AOP has gone from concept to verifiable engineering.

Fig. 4: Eye diagram of 112 Gbps (56 Gbaud PAM4) active transmission from the AOP sample, TDECQ 3.35 dB. Source: AIST × KYOCERA, ECTC 2026 - Fig. 4

3.3 This figure shows what the sample looks like — multi-chip ORDL routing

This figure (Fig. 3) is the actual sample: it includes Tx output, Rx input and external light source (ELS) input ports, with some dummy chips for simulated routing, and the center reserved for electrical components and the driver/TIA. Each chip has a 3000 µm-long upper mirror on one side, covering all optical I/O of a single chip. This shows ORDL routing and multi-chip placement can be co-designed, moving toward chiplet-class edge bandwidth density.

4. Technical Highlights

The first highlight is that the "embedded chip + 3D micro-mirror optical path" architecture has been actively lit up for the first time. Fully embedding the optics in the substrate and guiding light vertically with micro-mirrors on the chip's upper and lower sides effectively frees optical I/O density from the physical limit of fiber array pitch, while electrical connections use conventional short-trace packaging.

The second highlight is a process oriented toward volume manufacturing: 2PP 3D printing for the mold, UV imprinting to mass-produce micro-mirrors, and alignment by marks rather than high-precision chip embedding — turning optical microstructures into a repeatable, scalable process. The polymer ORDL handles both pitch conversion and routing to the substrate edge, leaving the optical connectors detachable at the edge.

5. Industry Link: How Far from Volume Production? Who Benefits?

Distance: this is the "architecture active validation" stage — a single sample lit up with signal meeting 400G specs, but there's still a way to go on full multi-channel loading, reliability qualification and yield. AIST's own follow-on reference points to a 1.6 Tb/s CWDM O/E converter (ECOC 2024), heading toward higher aggregate bandwidth.

Beneficiaries: most directly, the polymer ORDL and imprint/2PP equipment chain; next, packaging houses and IDMs that want to build chiplets on "embedded optical substrates" — AOP lets optical I/O and electrical chiplets be integrated on the same substrate using existing electrical packaging. The sober view: long-term high-temperature/high-humidity reliability of polymer waveguides, ORDL loss, and multi-chip yield remain the bottlenecks this route must clear.

6. Conclusion

The one sentence to remember from this paper: AOP is no longer slideware — AIST and KYOCERA have actually lit up a 3D optical path of embedded silicon photonics plus polymer ORDL, with 112 Gbps PAM4 and 3.35 dB TDECQ passing IEEE specs. For those following the battle of CPO routes, the thing to watch: the polymer ORDL embedded-chip route is moving from "passive loss demos" to "active transmission on spec"; the next thresholds are multi-channel operation, reliability and yield.

References

Fumi Nakamura, Akihiro Noriki, Kenta Suzuki, Satoshi Suda, Haruhiko Kuwatsuka (AIST) and KYOCERA, "Demonstration of an Optical Packaged Substrate with Embedded Silicon Photonic Transceiver for High Performance Chiplet Packaging," 2026 IEEE 76th ECTC.
National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan; KYOCERA Corporation, Kyoto, Japan