2026 OCP APAC Summit | PCIe 7 Makes Retimers Mandatory: Astera Labs on Where Copper Runs Out Beyond 128 GT/s

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PCIe 7's 128 GT/s keeps the same modulation, yet it doubles insertion loss per inch of trace while restoring the channel budget from Gen 6's 32 dB back to 36 dB. Together these lead to one outcome: in a complete CPU/GPU system, package loss, connectors, and PCB traces easily add up to more than 36 dB, so retimers officially go from "optional" to "mandatory". The key point of Astera Labs Senior Principal Product Manager Ryan Yue's talk at the OCP 2026 APAC Summit was not "optics will replace copper," but laying out the reach / power / latency trade-offs of four paths—passive copper, AEC, DSP optical modules, and LPO—and pinpointing where PCIe-SIG has truly changed the rules this generation: optical-aware retimers are now in the spec, the retimer limit per link rises from 2 to 4, and the SIG deliberately leaves the optical segment undefined. For Taiwan's supply chain, that "undefined" is where the opportunity lies.

1. The Bottleneck Is Not Frequency, but Loss per Inch

First, the drivers. Ryan Yue's first chart showed the annual growth of data generated—a CAGR of about 24%—followed by data center disaggregation: CPUs, GPUs, memory expansion, storage, and NICs are no longer packed together; they are placed apart. Placing them apart means longer electrical channels, and that is where every problem starts.

PCIe-SIG's cadence doubles bandwidth every three years: Gen 6 1.0 in 2022, Gen 7 1.0 in 2025, and Gen 8 expected in 2028. But the difficulty in these two generations comes from completely different places.

Gen 5 → Gen 6: Modulation moved from NRZ to PAM4, inherently bringing a signal-to-noise ratio (SNR) penalty of about −9.5 dB. To balance the budget, the SIG tightened the pad-to-pad insertion loss budget from 36 dB to 32 dB.
Gen 6 → Gen 7: Modulation stays PAM4, but the Nyquist frequency doubles, while the insertion loss budget is relaxed back to 36 dB.

It sounds like the budget got looser, but it's a trap. With the same PCB stack-up and the same traces, Gen 7 insertion loss per inch is roughly twice that of Gen 6. The budget gains 4 dB, but consumption per unit length doubles, so the net result is shorter achievable reach. The spec sheets board makers receive will look very ugly: tighter impedance tolerances, new connectors, redesigned backplanes—and the industry is now moving almost unanimously toward ADC-based DSPs.

2. Retimers Go from Optional to Mandatory

This is the single line most worth remembering from the talk.

Add up the losses of a real system—chip package loss, board connectors, motherboard traces, cable connectors—and the path from one GPU to one CPU easily exceeds 36 dB. Once it does, there is no debate about "whether to add a retimer," only "how many and where."

The impact on BOM structure is bigger than it sounds. Retimers used to be an extra cost paid to extend reach; now they are a prerequisite for a PCIe 7 system to boot at all. Meanwhile, switch radix keeps rising: today people look at 100-lane and 200-lane switches, and the speaker said we'll see 300-lane or even 700-lane parts. Doubling lane count means diagnostics and management complexity for every link, every port, and even every lane doubles too—signal integrity is just the first hurdle; link management is the real long-term cost.

Incidentally, every extra retimer or DSP adds power. It's no coincidence that "pJ/bit" came up again and again throughout the presentation.

3. Four Paths: Passive Copper, AEC, ODSP, LPO

Ryan Yue laid out four options; this was the most information-dense part of the talk.

Passive copper: typical reach about 3 meters, lowest power and latency, cheap but distance-capped. AEC (one retimer per end): about 7 meters, moderate power with DSP latency, the most cost-effective short-reach solution. ODSP optical modules (AOC): tens of meters with a practical upper bound of 30 meters, power up to 40 pJ/bit (including modules at both ends), higher latency, but the most robust and most compatible. LPO linear optics: long reach, about 20 pJ/bit, latency under 1 nanosecond, the lowest power and lowest latency.

A few points worth breaking out:

AEC is the most pragmatic short-reach answer today. A paddle card with a retimer at each end pushes passive copper from 3 meters to 7 meters while keeping the cost structure in the copper world. This also explains why AEC keeps growing in AI racks—we broke down the margin logic of this business in Earnings Highlights: Credo (CRDO) | Q4 FY26 — The Copper Cable Leader Turns "Reliability" into a USD 600M Optical Business.

Optics' 30-meter limit is not about the fiber. This was the most counterintuitive point of the talk: AOC distance is limited not by fiber attenuation but by PCIe flit latency. Run fiber too long, and round-trip latency forces you to design very deep replay buffers—a cost in hardware area and in performance. So the industry treats 30 meters as the practical upper bound not because light can't get there, but because the protocol math doesn't work.

ODSP's power cost comes from cleaning up after the optics. Reflections, dispersion, and nonlinearity in the optical channel all need DSP compensation, so tap counts are inevitably higher than in purely electrical DSPs, and power naturally stacks up to around 40 pJ/bit (including both end modules). LPO instead pushes signal-processing responsibility back to the host or switch SerDes; the module only does electrical-optical conversion, so it gets down to about 20 pJ/bit with latency below 1 nanosecond.

There's no free lunch. The power and latency LPO saves are borrowed from the host-side DSP—the host SerDes must be stronger and absorb the optical channel's complexity itself. This is the same conclusion as in After Copper Runs Out for AI: Seven Paths to Scale-Up Optical Interconnect and Two Ways to Live with Their Bottlenecks: there is no free reach, only costs that move to a different place.

4. The Rules PCIe-SIG Actually Changed This Generation

If you take away only one thing from this talk, take this.

Up to Gen 6, the SIG's rule for a link was: at most two retimers, both purely electrical. In Gen 7, the SIG made two changes:

Optical-aware retimers are included—a retimer may handle electrical-to-optical and optical-to-electrical conversion internally.
The retimer limit per link rises from 2 to 4.

The architectural flexibility this brings is real. The side of an optical-aware retimer facing the root complex (RC) and endpoint (EP) is still a purely electrical pseudo port—meaning the RC and EP need no special handling for "there's optics in the middle"; they still see a standard PCIe link. How the optics run in between is the retimer's own business.

The 4-retimer topology looks like this: one purely electrical retimer at each end extends on-board reach, and two optical-aware retimers in the middle handle electrical-optical conversion. The channel budget between RC and EP is thus split into more segments, each of which can use its full budget—opening up design freedom entirely.

But the most critical point: the SIG defines only the electrical side and deliberately leaves the optical side blank, as implementation specific. Modulation, wavelength, and transmission medium are each vendor's choice.

This is not laziness on the part of the spec writers; it is space deliberately left for the ecosystem—and precisely the gap Taiwan's supply chain can enter. At the same OCP event, another Astera Labs session by Jeffrey Kung, Optical Scale-Up Fabrics for Next-Generation AI Infrastructure, covered the flip side of the same story: when optics is absorbed into the fabric layer, whoever holds the conversion point holds the say over the spec.

5. LPO's Real Barrier Is Not the Optics, but Link Management

Astera has run both retimer-based optics and LPO topologies stably at Gen 6 in the lab, with very low BER. But the speaker spent a disproportionate amount of time on something unglamorous: to keep LPO healthy, you have to build the telemetry first.

The list is concrete:

Optical side: eye margining, readable eye diagrams, continuously monitored BER
Link side: a link retrain methodology aligned with the PCIe specification
PHY side: TX EQ coefficient tuning is still required; RX CTLE and DFE must stay at optimal settings
Initialization: LTSSM can still complete link training, but that's only the starting point

In other words, LPO saves power because it outsources "compensation"; the price of outsourcing is that you must be able to see the health of every element along the link, including the monitoring points defined by the LPO MSA. For this, Astera is pushing a link management software layer like COSMOS—able to seamlessly configure, monitor, and optimize every component on the link, beyond traditional TX/RX electrical tuning.

This view matches the conclusion of Winzer Nails the I/O Bottleneck of AI Clusters: the technical risk of linear optics has long since moved beyond the optical components themselves, to "who is responsible for proving at the system level that it's healthy."

6. How to Choose: Heterogeneous Means ODSP; Only Book-Ended Systems Get LPO

Ryan Yue's selection criteria are clean and worth copying straight into a design-review checklist:

Heterogeneous architectures—needing compatibility across multiple vendors, with uncertain channel characteristics: choose ODSP optical modules. Their DSP can absorb the unknowns; robustness is their value.
Book-ended architectures—both ends are your own, channel characteristics are fully known, and you want low power and low latency: LPO is a viable solution.

Add AEC for cost-sensitive short reach, and the selection map is complete: AEC wins on short reach and cost, ODSP on compatibility and longer reach (but expensive), LPO on power and latency (but requires you to own both ends).

None of them is a one-size-fits-all answer. That's why the speaker's closing call to action invited everyone to join OCP's Optics & Networking project to define the next-generation PCIe signaling topology and link management standards together—because there's no standard answer yet, and the spec vacuum is the window for positioning.

7. What It Means for Taiwan's Supply Chain

Three concrete positions:

First, the AEC window is longer than expected. PCIe 7's 7-meter AEC is not a stopgap; it is the only direct successor to 3-meter passive copper. Cables, paddle cards, connectors, retimer packaging and test—this entire chain still has volume through 2026–2028. Taiwanese vendors' positions in high-speed cables and paddle card assembly don't need to be rebuilt; they just need to keep up with 128 GT/s process and test requirements.

Second, by leaving the optical side "undefined," the SIG hands implementation of the optical engine back to the market. With modulation, wavelength, and medium all implementation specific, the design and packaging of the optical engine inside an optical-aware retimer—PIC/EIC integration, fiber coupling, FAU, laser source—are not locked down by the spec. For Taiwanese vendors already positioned in the CPO supply chain, this is an extension, not a new problem.

Third, test and telemetry are the truly underrated piece. When one link may carry four retimers, each needing independent margining, and lane counts head toward 700, per-lane diagnostic capability will become a hard criterion for system makers choosing suppliers. This is an opportunity for Taiwan's ATE, probe card, test instrument, and firmware teams—and its moat is deeper than that of mechanical parts.

Conclusion

This keynote did not proclaim "optics replaces copper," and that is what makes it most credible.

The real state of PCIe 7: copper isn't dead, but it's been squeezed to within 7 meters; optics has entered the spec, but only halfway—the electrical half has a standard, while the optical half is up to each vendor. The gap left in between is the battlefield where the supply chain gets reordered over the next two years.

If you're a system architect, the action items are clear: budget retimers into the BOM as mandatory, treat 30 meters as the practical upper bound for optics (because the limit is flit latency, not fiber), and before choosing LPO, ask yourself: can I prove this link is healthy? If you can't answer, use ODSP first.

If you're in the supply chain, the signal is: what's truly scarce is not the ability to build optics, but the ability to manage them.

This article is for technology and industry trend analysis only and does not constitute investment advice.