TSV is too expensive and glass can't embed dies, so Singapore's national team turned to mature fan-out packaging (FOWLP) for a 1.6T silicon photonic engine. Coupling loss < 2 dB, wafer-level automated testing and direct-drive friendly — the CPO race is shifting from “can it be built” to “who can build it cheaply.”

Edgecore admitted 1.6T LPO is "not yet successful," so the stopgap is gone and CPO can no longer wait a generation. Three MSAs at OFC 2026 push CPO toward swappable engines, while SONiC only now has the models it needs. Hardware decides who ships; software decides who deploys at scale.

PCIe 7 keeps PAM4 but doubles insertion loss per inch, turning retimers from optional to mandatory. Astera Labs laid out the reach and pJ/bit trade-offs of AEC, ODSP and LPO, and noted that PCIe-SIG deliberately leaves the optical side undefined—where supply chain positioning happens.

Semtech moved its full-year data center growth language from "at least 50%" to "no cap." More telling than the $291M in revenue: 1.6T, CopperEdge and HieFo all ramp together in the second half, and "capacity is king" is becoming the deciding factor of this optical cycle.

Compute grows 75% a year; the copper feeding it grows only 20%. That scissors gap is the root of AI infrastructure pain. Winzer uses six figures to complete the causal chain for linear optics, and lands on a sharp conclusion: this generation's ceiling is the 1 meter of scale-up copper.

1.6T is a generational shift up from 800G. Tear down both modules side by side: DSP goes from 80 to 130, each light source costs 3-4x more, and SiPh penetration rises from 40-45% to 60%. See where cost jumps, how the bottleneck moves, and who takes the margin.

At OFC 2026, Amphenol showed its vision for AI data center interconnect: the XPO module packs 8x the density of OSFP with built-in liquid cooling, challenging CPO's lead as the industry moves from 224G to 448G.