2026 OCP APAC Summit | Microsoft | Gohar Waqar, Sushant Gupta | From Silicon to Systems
Microsoft's keynote at OCP APAC appeared to be a showcase of in-house silicon (Maia 200, Cobalt, Azure Boost DPU), but the real message was a public "bottleneck shift" announcement: the limiting factor for AI infrastructure has moved from the accelerator itself to power delivery, cooling and networking. For Taiwan's supply chain, Microsoft saying that "roughly 70% of cloud hardware components come from Taiwan and the APAC ecosystem" sounds flattering, but what it really means is this: 70% supply share is just an entry ticket. The money is flowing toward the "system-level co-design" layer, and anyone who can't get into it will keep making components whose margins get squeezed.

1. Why now: the demand curve has outrun the technology
Microsoft didn't open with a vision statement. It opened with three sets of numbers, and every one of them says the same thing: demand is growing faster than technology can keep up.
First: data center power demand will grow from about 100 GW in 2026 to more than 400 GW by 2030, a 4x increase in four years.
Second: AI-related investment swells from about US$71 billion in 2022 to US$1 trillion in 2027.
The third is the most important: as workloads move from large language models to agentic systems, scale has grown roughly 6,000x in recent years, far outpacing what compute, memory and storage can keep up with.
Put these three numbers together and Microsoft's point is clear: the problem is no longer "build a faster accelerator", but whether the economics of the entire infrastructure can sustain this pace of expansion. As deployments jump from megawatt scale to gigawatt scale, the hard part isn't fitting hardware into the data center; it's making this "scale sustainably" in economic and energy terms. That set the tone for the whole talk, and everything that followed hangs on this statement.
2. Silicon-to-Systems: Microsoft turns in-house silicon into a whole system, not a single chip
Microsoft's answer is called silicon-to-systems: rather than betting on a better chip, a faster network or a more power-efficient data center alone, it co-designs silicon, platforms, networking, data centers, plus security and sustainability, as one whole.
In-house silicon is the starting point of this logic, and Microsoft laid out three chips this time:
Maia 200: Microsoft stressed that it was never meant to be a standalone chip, but part of a complete AI system designed together with the models, network, software and data center. On paper it delivers 30% better tokens-per-dollar than the previous generation and 1.4x performance per watt; Microsoft specifically noted that these figures were validated on real GPT-5.5 workloads, not synthetic benchmarks, and it is already running Microsoft 365 Copilot.
The second in-house CPU (transcribed as "Core 200", corresponding to Microsoft's Cobalt CPU generation): positioned as an "agent-native CPU" built for the new demands of agentic workloads: agent interaction, task orchestration, data retrieval, memory management and service calls, all of which need to run fast and efficiently. It is another example of "designing hardware around emerging workloads".
Azure Boost DPU: offloads CPU-hungry work such as storage data compression, network transactions and security functions onto a dedicated platform, claiming up to 4x performance with lower power, plus higher storage density and hardware-rooted trust.
Taken together, the three chips are meant to prove one position: at AI scale, a chip's value lies not in its standalone specs but in whether it sits inside a system co-designed from the ground up.

3. The real signal: the bottleneck has moved from chips to power and heat
If you only look at the in-house silicon, you'll miss the most important line of the keynote: "As AI scales, the bottleneck is moving beyond compute itself." Microsoft was blunt: going forward, the limiting factors are power delivery, cooling capacity and data center efficiency.
On power, Microsoft said it is re-architecting power delivery all the way from the grid to the rack (grid-to-rack), citing technologies including high-temperature superconductors, solid-state transformers, and a distributed off-grid power system called Mount Diablo. On cooling, it is investing in microfluidics and next-generation heat exchange units.
This is a wake-up call for Taiwanese companies used to making "components": a large chunk of the next wave of AI infrastructure capex will flow into power and thermal management, not just circle around accelerators. Cooling is moving from air to liquid and on to chip-level microfluidics, and every node along that path (cold plates, quick disconnects, CDUs, heat exchange) is a new position to claim. We laid out the numbers behind the technical and cost tension at this stage in 51.2T NPO switch cooling: an 835W ASIC plus 16 optical engines, air or liquid?.
4. Networking becomes the new definer: from scale-up to scale-across, all on the OCP open path
Microsoft positions networking very highly: AI infrastructure is "increasingly defined by the network". When models depend on hundreds or thousands of accelerators communicating efficiently, success hinges on bandwidth, latency, reliability and power.
It split networking into two layers. The first is scale-up: high-density interconnect between accelerators inside the rack, where bandwidth, latency, reliability and power directly determine system performance. The second is scale-across: linking multiple AI clusters so they operate as a "single AI supercomputer". Microsoft repeatedly stressed that both layers must be driven through open organizations such as OCP, using open architectures, not built behind closed doors.
This lines up exactly with the dominant theme in the optical communications supply chain over the past six months. Why copper can't hold up at scale-up and the job must ultimately go to optics, and which optical interconnect technology paths are colliding, we covered in After copper gives out for AI: seven paths for scale-up optical interconnect; and for the energy-efficiency battlegrounds and pJ/bit ceilings of the scale-up, scale-out and scale-across networks, OIF has drawn an official map, see OIF draws an official map for AI interconnect: three networks, one pJ/bit battlefield. Microsoft's keynote effectively upgrades that map from a standards body document into a hyperscaler's procurement roadmap.
"Open" is not a slogan; it's a procurement signal. Whoever helps set the standards in the OCP room gets the design-in first. AMD already played out this logic at Advancing AI when it wrote "open Ethernet" into the rack backbone; for context see AMD writes "open Ethernet" into the rack backbone.
5. The counterargument: this is not a "Microsoft ditches NVIDIA" story
The in-house silicon numbers look great, but don't over-read them. In the same segment Microsoft talked about "customer optionality": no single architecture can efficiently serve every AI workload, so Azure offers both "industry-leading partner solutions" and its own 1P silicon, letting customers choose by training, inference and cost goals. In plain terms: Maia is there to fill gaps, push down costs and give Microsoft negotiating leverage, not to replace GPUs.
The most honest evidence is the agenda itself: right after the silicon-to-systems talk, Microsoft's next move was "welcoming NVIDIA's CEO to the stage". A company that makes a compelling case for its in-house silicon, then immediately hands the stage to the GPU leader, tells you where 1P silicon really sits in overall shipments: important, but still a supporting role.
So the supply chain implication should be read the other way around: rather than betting on whether Maia can beat GPUs, recognize where the money flows. What will definitely scale are the system layers needed no matter whose chip wins: power, cooling, networking, optical interconnect and racks. Who wins among accelerators is a variable; the scaling of the system layer is a constant.
Conclusion: Taiwan's 70% supply share is just an entry ticket
Microsoft was clear: since 2020, its investment in APAC has grown about eightfold; today roughly 70% of its cloud hardware components come from Taiwan and the APAC ecosystem; and it specifically named Taiwan as a global hub for semiconductor innovation and advanced manufacturing, and one of Microsoft's most important strategic partners.
Take the compliments, but understand the other side. 70% is an entry ticket, not a moat. What this keynote said from start to finish is that value is moving from "components" to the "system-level co-design" layer: power (solid-state transformers, superconductors), cooling (microfluidics, liquid cooling, heat exchange), networking and optical interconnect (scale-up/scale-across), and rack system integration. The words Microsoft kept using were co-design and collaboration, all under the open OCP framework.
So Taiwan's supply chain faces just one question: are you treated by Microsoft as "a contract pool making 70% of the components", or are you named into the OCP room as a system partner that sets standards and co-designs with them? The former will see margins ground down by scale and price comparison; only the latter gets a share of the capex spilling over from accelerators into power, cooling and optics. Companies that can climb from "supplying components" to "co-designing systems" (whether they make CDUs and liquid cooling, solid-state transformers and power supplies, scale-up optical engines and CPO, or are EMS players doing rack integration) are the real winners in this silicon-to-systems narrative. Everyone else can keep counting that 70%.
This article is for technology and industry trend analysis only and does not constitute investment advice.
Related reading
CPO is no longer "crying wolf": six real signals from the LightCounting CPO/NPO conference: Microsoft is betting optical interconnect on the OCP open path, and CPO's volume-production signals point in exactly this direction.
When XPU heat sits right on the photonic chip: imec quantifies the thermal cost of 2.5D/3D CPO in 18 charts: as cooling becomes the new bottleneck, the thermal cost borne by photonic chips is an unavoidable lesson.
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