AMD Writes "Open Ethernet" Into the Rack Backbone: What Advancing AI 2026 Really Signals for the Optical Supply Chain
On the surface this keynote was about GPUs and CPUs, but for the optical communications supply chain the real story hides in three places: the network layering of the Helios rack, AMD choosing "UALink over Ethernet" for scale-up instead of a closed copper backplane, and the MI500 roadmap listing "optical interconnect" as a headline spec for the first time.
AMD has taken the "open Ethernet" side. Helios uses UALink over Ethernet (UALoE) for scale-up and Ultra Ethernet + the Pensando Vulcano 800G NIC for scale-out, so the whole fabric runs on open standards and a merchant supply chain. Structurally, that favors merchant players in optical modules, DSPs, and laser sources far more than a closed copper-backplane approach.
Demand scale is no longer the question. OpenAI at 6GW, Meta at 6GW, Anthropic adopting Helios for the first time — plus AMD raising its data center AI accelerator TAM to US$1.4 trillion by 2030. All of that ultimately converts into 800G / 1.6T optical module shipments.
The optical interconnect timeline is now official. The MI500 (2027) roadmap explicitly lists "new copper and optical interconnects" and a "larger scale-up domain." This is the clearest signal yet that optical I/O is moving from between racks (scale-out) to inside the rack (scale-up).
But don't get the timing wrong. Today's scale-up is still copper territory (UALoE inside the rack). The near-term optical upside is in front-end and scale-out; scale-up optical interconnect is a post-2027 story that tracks MI500 / CPO progress.
1. Why Now: Why a "GPU Launch" Is Worth Watching to the End If You Work in Optics
AMD's Advancing AI 2026 ran for two hours with round after round of hardware. Most coverage will focus on the MI455X's 34x inference throughput over the previous generation, Venice's 256 CPU cores, or OpenAI, Meta, and Anthropic sharing the stage.
But if you sit in the optical supply chain, the keynote's value isn't in those headline numbers — it's in a line Lisa Su kept repeating that's easy to miss: AI is no longer a chip or server problem; you have to "design the entire rack as one system," and even "treat the entire data center as one system."
When the unit of compute scales from "server" to "rack" to "data center," the interconnect between chips, between racks, and between buildings goes from supporting role to lead. And once interconnect has to exceed the reach and bandwidth copper can handle, optics is the only answer. That's why a GPU launch is actually a must-watch event for anyone selling optical modules, DSPs, TIAs, or lasers.
2. Breaking Helios's Network Into Three Layers: Where Is the Optical Module Battlefield?
To judge what this launch means for optics, you first have to understand how the network of Helios, AMD's "AI rack," is layered. AMD's deck splits it cleanly into three parts:
Front-End: Handled by the Salina DPU paired with an 800G AI NIC, covering external traffic, SDN, and storage. This is an extension of traditional data center networking — and a market where 800G optical modules are shipping right now.
Scale-Out: Connections between racks and between clusters, handled by the AMD Pensando Vulcano 800G NIC on the open Ultra Ethernet (UEC) standard, with Broadcom Thor Ultra named as also supported. This layer is the core market for optical modules — once distances stretch, copper exits; it starts at 800G and moves toward 1.6T. AMD stressed that Helios offers 50% more scale-out bandwidth than its rival, which in plain terms means more optical modules packed into every rack.
Scale-Up: Inside the rack, dozens of GPUs are bound into one large memory domain; AMD uses UALink over Ethernet (UALoE). This layer is still mostly copper today (short in-rack distances that copper can still handle), but it is precisely this layer that will determine whether optical interconnect can penetrate further over the next few years.
In one sentence: front-end and scale-out are orders optics can capture today; scale-up is the upside for the next year or two. The three layers differ in bandwidth, reach, and standards, and so do the corresponding optical component specs — don't lump them together when analyzing AI racks.
3. AMD Chose "Open Ethernet" as the Backbone — Good News for Merchant Optics
The most structurally significant takeaway from this launch for the optical supply chain isn't any single number — it's which side AMD took.
NVIDIA's scale-up runs on its proprietary NVLink closed copper backplane, which is relatively hard for optics to break into. AMD laid out its position plainly this time: scale-up on UALink over Ethernet, scale-out on Ultra Ethernet, and the entire fabric on open standards and merchant silicon wherever possible. Lisa Su repeatedly emphasized an "open ecosystem" on stage, and Helios's networking tray even "uses partners' silicon to connect the GPUs."
No single company can do it all — this is a chance to bring the strongest players together.
For the optical industry, the implications of the open Ethernet path are straightforward:
A bigger, more contestable order pool. A closed backplane locks interconnect into a single supplier; open Ethernet gives merchant optical module, DSP, light source, and switch silicon vendors a shot at winning designs. AMD's path is essentially growing the pie for the entire merchant optical ecosystem rather than locking it up.
Specs converge on Ethernet. Going with UEC / UALoE means optical module specs will evolve along Ethernet generations (800G → 1.6T → 3.2T). That's a tailwind for a supply chain already betting on Ethernet optics, and pressure on players hoping to open a new front with proprietary interfaces.
4. MI500 Makes "Optical Interconnect" a Headline Spec: The Timeline Is Official
If the previous sections were trend reading, this one is hard evidence.
AMD unveiled its multi-year Instinct roadmap: MI350 Series (now) → MI400 Series → MI500 Series (2027) → MI600 Series (2028, CDNA Next). In the MI500 box, AMD explicitly lists three highlights: next-generation HBM, a larger scale-up domain, and "new copper and optical interconnects."
Optics people should underline this twice. First, a "larger scale-up domain" means binding more GPUs into a single memory domain — and once that exceeds the reach and bandwidth copper can support, optics has to come in. Second, AMD wrote "optical interconnects" directly into the MI500 spec list — the clearest vendor-level timing statement yet that optical I/O is entering accelerator scale-up interconnect: not a 2030 vision, but a 2027 product.
Another MI500 slide makes it even more vivid: AMD says MI500 will deliver the biggest generational leap in Instinct history, compounding inference throughput by more than 2,000x over four years. Feeding that level of compute density requires memory bandwidth to keep up — and interconnect bandwidth even more so. That next step up in interconnect is optics' opportunity.
5. Converting GW Into Optical Modules: Demand Scale Is No Longer the Question
The most common debate in optics over the past two years has been "how real is the demand?" This keynote all but laid the answer on the table.
AMD raised its 2030 data center AI accelerator TAM to US$1.4 trillion (a CAGR of roughly 45%) and said outright that last year's "US$500 billion by 2028" now looks conservative. Even more important are the actual customer commitments: OpenAI has committed to deploy up to 6GW of AMD infrastructure, Meta up to 6GW (starting with MI450), and Anthropic is adopting Instinct and Helios for the first time.
GW is the most honest unit of demand. Every GW of AI racks corresponds to hundreds of thousands of high-speed optical interconnect ports. When three frontier labs all size their deployments in GW, and Helios is designed on an annual cadence with a new generation every year (Helios → Helios 500 → Helios 600), optics isn't looking at a one-off inventory pull but at a predictable multi-year demand curve that steps up year after year.
Sachin (OpenAI) repeating "I need more compute" on stage wasn't a joke — every time "more compute" stacks up, another line gets added to the order books for optical modules, light sources, and DSPs.
6. Another Thread: Disaggregated Inference and Cerebras Amplify "Rack-to-Rack Traffic"
There's another thread that's easy to overlook but equally important for optics: disaggregated inference.
AMD noted that the inference market is stratifying, and for the "ultra-low-latency" segment the best solution is to split prefill (compute-hungry) and decode (memory-bandwidth-hungry) onto different hardware and run them separately. AMD and Cerebras are partnering on a solution that pairs Helios racks with Cerebras wafer-scale engines.
What's the cost of splitting them up? More data movement across nodes and racks. Prefill results have to be fed to decode, and all of that traffic must be carried by the network. The more inference moves toward "disaggregated, distributed, ultra-low-latency," the greater the interconnect pressure between racks — which is exactly scale-out optics' home turf. In other words, agentic inference doesn't just increase token volume; it also lengthens the distance tokens "run back and forth" between hardware — and both favor optics.
7. Risks and Counterarguments: Don't Confuse "Will Happen" With "Is Happening Now"
STT never does one-sided optimism. This keynote is a tailwind for optics, but three things call for a cool head.
First, scale-up is still copper territory today. UALoE remains mostly copper inside the rack, and MI500's optical interconnect won't land until 2027. The very phrasing "new copper and optical" shows that AMD isn't switching to optics in one step — copper will hold on for in-rack short reach for a while. Optics entering scale-up is a trend, but not tomorrow's reality.
Second, the open-standards battle isn't over. UEC (Ultra Ethernet) and UALink are both still evolving rapidly. Multi-vendor support sounds great, but standards convergence, interoperability validation, and yield ramps all take time. The GW figures and generational cadence on the roadmap are "plans," and the deck's disclaimer page states in black and white that "timelines and product specifications are subject to change."
Third, this keynote didn't spell out CPO's place. AMD talked about scale-up optical interconnect but didn't lay out the timing for Co-Packaged Optics (CPO). Will optical I/O follow a pluggables-first, CPO-later path, or jump straight to CPO? The keynote gave no answer — and that fork will determine whether the pluggable camp benefits first or the CPO supply chain locks in position first over the next few years.
Factor in these three points and the read is complete: the direction is clear (open Ethernet, optics penetrating scale-up, GW-scale demand), but the timing must be broken down by year — front-end / scale-out today, scale-up optical interconnect a year or two out.
Conclusion
What AMD's Advancing AI 2026 delivered to the optical supply chain wasn't a number but a choice of side: betting the rack backbone on open Ethernet (UEC + UALoE) and, for the first time, writing "optical interconnect" into the MI500 roadmap as a formal spec. For merchant players in optical modules, DSPs, and laser sources, this path is friendlier than a closed copper backplane because it grows the interconnect pie and keeps it open to competition.
If you take away one actionable judgment from this keynote: read order timing in two layers. Near term (2026), watch 800G / 1.6T pluggable optical module shipments for front-end and scale-out — the volume GW-scale deployments need right now. Longer term (2027 onward), watch whether MI500's scale-up optical interconnect and CPO get named — that's when the big narrative of optics "penetrating inside the rack" truly pays off. AMD has stamped the direction; what remains is the timing.
This article is for technology and industry trend analysis only and does not constitute investment advice.
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