2026 OCP APAC Summit | ASE | Nicole Tien | Inside the Package: What Holds CPO Back Isn't the Optics, It's the Testing Nobody Wants to Talk About

2 days ago

8 min read

In this keynote ASE presented a very clean three-step energy-efficiency breakdown: pluggable optical modules top out at 1.6 Tbps and 10 pJ/bit; Co-Packaged Optics (CPO) reaches 12.8 Tbps at about 5 pJ/bit; and only by 3D-stacking the optical engine to shrink distances to the minimum is there a chance to get below 3 pJ/bit.
Packages have already been stretched to 120 × 120 mm, and the package area required for high-bandwidth memory alone has grown 7.5x in ten years. CPO is not "squeezing one more optical engine into the package"; it redraws the entire package map.
The most valuable line of the session was not a spec but a complaint: Nicole Tien said outright that almost nobody at the event was talking about Known Good Optical Engine (KGOE) testing. What holds CPO back on the way from demo to mass production is not optical design; it is yield and test.

1. An OSAT Comes to OCP, and the Topic Is Influence, Not Capacity

The OCP stage has always belonged to system vendors and chipmakers. Broadcom talks Ethernet, NVIDIA talks AI factories, Arista talks about how long pluggables can last. When an OSAT takes the stage with a talk titled "Inside the Package," that in itself is a signal.

ASE's presence at OCP has clearly intensified in recent years. At the same Summit, CP Hung also gave a talk on the integration roadmap (which we broke down in AI Hardware's Next Battlefield Is Packaging, Not Process: Breaking Down ASE CP Hung's "Integration Trilogy"). Nicole Tien's talk pushes the camera much closer: not trends, but what actually happens inside the package.

Her opening framework was AI's four layers of scaling: scale-in (inside the XPU/ASIC), scale-up (in-rack interconnect), scale-out (clusters) and scale-across (between data centers). This layering is now practically the industry's common language, but the conclusion she drew is very OSAT: every layer you climb eventually comes back to "can this package be built?"

2. Three Axes Hitting Their Limits at Once

She used a three-axis chart to describe the current predicament: chip, package and system.

Chip axis: from 180 nm all the way to 2 nm, the Moore's Law curve can no longer keep up with AI's appetite. Chiplets and heterogeneous integration are taking over.
Package axis: starting from fan-out SiP in smartwatches a decade ago (more than a thousand components in a single package, active ICs plus GPU and memory, like complex LEGO), building up to today's 2.5D/3D integration.
System axis: power came first (VRMs into the package, power SiP, backside power delivery), and only then PICs and switch chips, i.e., silicon photonics CPO.

There is an easily overlooked ordering here: optics is the last thing to move into the package. Power, memory and chiplets have already fought their battles inside the package; the optical engine is the newest and most fragile tenant. She put it plainly: optical engines are very fragile.

Within four years, every requirement must grow more than 4x, and the CPO market itself is also projected to grow 4x. Current packaging solutions have already reached 120 × 120 mm. This is not incremental evolution; size and complexity are both running away at the same time.

3. From 1.6T to 32T: The Three-Step Energy-Efficiency Math

The most useful slide of the session was a direct comparison of three architectures:

Conventional pluggable optical module: 1.6 Tbps / 10 pJ/bit
CPO (optics moved next to the chip): 12.8 Tbps / about 5 pJ/bit
3D die-to-die stacking plus optics: 32 Tbps and above (official abstract figure) / target below 3 pJ/bit

Nicole Tien used LEGO to explain the progression: rather than laying things out flat, stack them upward, because shorter distance means bandwidth and energy efficiency. The idea itself is not new; what makes it valuable is that she put the three sets of numbers side by side. Going from 10 pJ/bit to 3 pJ/bit is more than a 3x efficiency gap, and every step comes at the cost of packaging complexity.

It also answers a common question: is CPO really necessary? By ASE's math, the pluggable ceiling is 1.6T at 10 pJ/bit, and no other solution can raise bandwidth by an order of magnitude while cutting power in half. We derived this limit in full in Have Pluggable Optics Hit the Wall? Understand This Limit Before You Understand CPO.

One more number deserves its own callout: in 2026–2027, the package area needed for high-bandwidth memory is already 7.5x what it was ten years ago. That means the fight for space inside the package is not CPO's problem alone; for the optical engine to move in, it has to compete with HBM for the same real estate.

4. The VIPack Toolbox: CPO Is a "New Arrangement of Existing Technologies"

ASE places CPO under its VIPack platform. The six pillars run from fan-out PoP, fan-out SiP on package (in volume production for automotive radar for more than fifteen years) and 2.5D/3D IC, through FOCoS bridge with interposer, and finally CPO.

The key toolbox specs she listed were among the few hard numbers in the session:

Multi-die integration with a die-to-die spacing of 50 μm
Double-sided RDL that can include passives; AI projects can currently add an extra 6P6M of RDL layers
Interlayer copper pillars 150 μm tall at a pitch of 120 μm
TSV integration with stress-mitigated vias
Ultra-low-loss interconnect and hybrid bonding

The point of this spec list is not how advanced each item is, but that all of them are existing, proven technologies. ASE's argument is that CPO does not need a brand-new process; it rearranges mature packaging technologies. That is the best possible narrative for an OSAT, because it shifts the answer to "who can do CPO" from "whoever has the best optical design" back to "whoever has the deepest packaging process database."

We discussed this shift in The CPO Ecosystem Is Being Reshuffled: Foundries and OSATs Move from Supporting Roles to Lead Roles. In this talk, ASE essentially stood on stage and made that argument itself.

5. The Real Hurdles: Fiber, Warpage, and the Testing Nobody Wants to Talk About

In the second half she laid out CPO's mass-production obstacles, which can be summed up in two words: fragile and hard to test.

Fiber attach. Detachable and non-detachable approaches are still competing; her observation is that "the industry currently still prefers detachable solutions." On coupling, edge couplers, grating couplers, active alignment and passive alignment are all still on the table, and ASE leans toward top-side coupling plus wafer-level package assembly and test. The reasoning is simple: anything that can be done at wafer level should not be left to package level. For the competitive landscape at this step, Fiber-to-Chip: The Least Sexy Step in CPO That Is Holding Everyone Back has a fuller vendor rundown.

Warpage control. The larger and thinner the package, and the bigger the CTE mismatch between materials, the more lethal warpage becomes. Her solution is at the process level: mass reflow or thermal compression bonding (TCB), a rare explicit endorsement of TCB in the CPO context.

Testing, required at four stages:

Wafer-level test of the EIC/PIC: only known good dies can go into the package
Chip-on-wafer test: dies must be tested again after being bonded to the host wafer
Standalone optical engine test: the last gate before the three components are integrated
Double-sided test

Then she delivered the most honest line of the event: Known Good Optical Engine testing is something almost nobody at this event is talking about.

That line deserves amplification. The economics of CPO are fundamentally a yield problem: a 120 × 120 mm package carries the XPU, HBM and optical engines, and if any single component is found bad only at final test, the entire package is lost. A failed pluggable module is simply swapped out; a failed CPO means replacing the heart of the whole switch. So KGOE is not a test engineer's detail; it determines whether CPO unit cost can converge. Right now, the ecosystem's attention to this issue is clearly far below its importance.

6. Her Call to Action Was Really Saying "The Ecosystem Isn't Ready"

At the end, Nicole Tien did not talk about ASE's capacity or customers. Instead she issued a four-quadrant appeal: stress and simulation, performance, power, and test solutions, four problems that need the key ecosystem players to come in and solve together. Her words were unusually direct: the ecosystem actually is not ready.

When the leading OSAT says on the OCP stage that the ecosystem isn't ready, there are usually two readings. The optimistic one: it is a recruiting call for EDA, materials, equipment and test-equipment partners to build the standards together. The pragmatic one: it is managing customer expectations; the CPO mass-production timeline cannot be signed off yet.

I lean toward the latter, but that is not bad news. The truly dangerous signal would be everyone saying they are ready and then quietly bleeding on yield. ASE choosing to raise the alarm publicly on testing means it has already located that bottleneck.

7. What It Means for Taiwan's Supply Chain

The signals for Taiwan's supply chain are actually quite concentrated:

Test and measurement is the most underrated link. Of the four test stages, standalone optical engine test and double-sided test still lack mature standard solutions. Vendors of optical metrology, probe cards, alignment fixtures and burn-in testing will see structural demand over the next two years. This is not riding the "AI concept" wave; it is a real additional step in the process flow.

The window for FAU and coupling solutions is still open. ASE said explicitly that the industry still prefers detachable fiber and leans toward top-side coupling with wafer-level assembly. Taiwanese companies with a track record in fiber array units (FAU) and coupling structures are still on the evaluation list; the route has not been locked in.

Packaging materials and warpage control are a hidden race. The mention of mass reflow and TCB means "unsexy" materials links such as package substrates, underfill and stress-mitigation structures will be repriced.

But the counterpoints deserve a sober look too. ASE's 12.8 Tbps / 5 pJ/bit is a platform capability, not volume next year. The session gave no mass-production timeline, no customer names and no yield numbers, and its most honest line was still "the ecosystem isn't ready." Treating this talk as evidence that "CPO is about to explode" overreads it; treating it as evidence that "CPO's bottleneck list has shifted from optics to test" is accurate.

8. Conclusion

If you keep only one sentence: CPO's technology debate is over; we are now in the yield debate.

The bandwidth and efficiency math is crystal clear: from 1.6T at 10 pJ/bit to 12.8T at 5 pJ/bit and then below 3 pJ/bit, the roadmap is not in dispute. The toolbox is ready-made as well: 50 μm die-to-die, double-sided RDL, TSV, hybrid bonding, all technologies proven in volume. The only question left unanswered is how you know the optical engine is good before it goes into the package.

The Known Good Die concept has been around in semiconductors for thirty years. What CPO has to do is tell that story again, this time with light as the protagonist. The next signal worth tracking is not who announces how many Tbps, but who is first to publish KGOE test yield.

This article is for technology and industry trend analysis only and does not constitute investment advice.