2026 OCP APAC Summit | TSMC Says It Plainly: Advanced Packaging Is the Gatekeeper of AI Compute, and the Era of Component-Level Qualification Is Over

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At OCP, TSMC advanced packaging head Jun He appeared to be walking through the 3DIC technology roadmap, but the real message boiled down to one sentence: component-level qualification is no longer enough. When AI products move on an annual cadence and customer chips enter the fab before TSMC's own test vehicles, packaging is no longer a back-end assembly step. It is the gatekeeper that decides whether AI compute can ship at all. What TSMC wants is to pull the entire supply chain (substrates, materials, equipment, HBM, system integrators) out of their separate silos and into a framework called STCO (System-Technology Co-Optimization), forcing everyone to sit next to the fab and co-optimize together. And the line buried mid-talk, that "signaling is far more power-efficient with photons," amounts to TSMC endorsing CPO and silicon photonics on stage.

1. Why Now: An OCP Talk That Was Really TSMC Throwing Down the Gauntlet to the Systems Camp

Start with who was speaking. Jun He runs TSMC's Advanced Packaging Technology and Service, the organization that took over TSMC's back-end operations three years ago and now holds ten advanced technologies. Speaking at OCP, a venue packed with system builders, he opened by lowering his own profile, saying "I represent not only TSMC but the whole silicon IP and packaging ecosystem," and then made a direct appeal: the component world and the system world must collaborate much more closely, and they must do it "now."

This was not politeness. For more than a decade TSMC has had the final word on the chip side thanks to process leadership. But once 3DIC moved the battlefield from "inside one chip" to "an entire packaged system," TSMC found that it could no longer see the system-level boundary conditions. The word that kept coming up in the talk was co-optimization. In plain terms: TSMC admits it cannot package what customers need on its own; it needs the systems camp to spell out exactly how their systems will stress this package.

When a company whose creed is process leadership starts publicly asking downstream partners for "system feedback," the rules of the game have changed.

This is not the first time the issue has surfaced. We already broke down why CPO is fundamentally an advanced packaging war in Why CPO Is an "Advanced Packaging" War; this OCP talk is TSMC stepping on stage to put its own stamp on that argument.

2. Advanced Packaging Is Now the Gatekeeper of AI Compute: The Two Scaling Curves of CoWoS and SoIC

Why does TSMC feel confident enough to call out the systems camp? Because packaging is now the bottleneck, and whoever owns the bottleneck speaks loudest. The talk laid out two scaling curves that could hardly be more concrete:

The CoWoS line (including InFO 2.5D): TSMC is already in volume production of packages at 5.5x reticle size, with 98% and sometimes 99% yield on multiple AI customer products. The roadmap is a new CoWoS generation every year, reaching 14x reticle size by 2029. Going from 5.5x to 14x enlarges a single package's "real estate" by another 2.5x, fitting in more compute dies and more HBM.

The SoIC line (true 3DIC via hybrid bonding): more than 50x the interconnect density and 5x the energy efficiency. TSMC entered volume production last year at a 6 μm hybrid bond pitch, and by 2029 it aims for a 4.5 μm pitch, stacking A14 directly on A14 (advanced node on advanced node).

Put those two numbers side by side and the point is not "TSMC is strong." It is that this level of complexity is a disaster for yield. Jun He himself compared CoWoS to conventional lithography and said bluntly that "the statistics are against us": every order-of-magnitude increase in feature complexity amplifies the probability of defects, and every finished CoWoS unit carries enormous economic value, so each scrapped unit is real money. Yield is no longer a process metric; it is the precondition for the business to exist at all. That is why TSMC can call packaging the gatekeeper: what it guards is not technology but the ability to build AI chips at an acceptable yield.

For TSMC's full system integration blueprint, our figure-by-figure walkthrough in Breaking Down TSMC's 3.5D System Integration Blueprint at VLSI 2026 covers the technical details for readers who want to go deeper.

3. STCO: Component-Level Qualification Is Dead, and TSMC Wants the Supply Chain Right Next to the Fab

The real "money slide" of the talk was Jun He describing how the development model is changing. Technology development used to be a relay race (silo): lock the process first, validate on a test vehicle, then hand off to customers. That no longer works because, in his own words, "customer products will enter the fab before my test vehicle, even before the process is locked".

The annual cadence squeezes timelines to the limit, so TSMC has switched to parallel development: technology teams, manufacturing teams and customers all working together at the same time, deep inside the volume-production fab, fixing things as they go. That brings a requirement with huge consequences for the supply chain: materials suppliers, equipment vendors and system integrators all have to station "boots-on-the-ground-level expertise" next to the fab to keep up with this pace.

Jun He made two concrete requests, the most actionable part of the entire talk:

First, six quarters before mass production (MP), TSMC will publish boundary conditions and then collect feedback, ensuring that what is delivered at process lock is what the system actually needs. Second, there must be a continuous system feedback signal throughout development, so that any anomaly on the system side can be acted on immediately. He even cited a painful case: the same chip placed into different systems showed no problems at component level, yet at the customer it exhibited chipping and spreading low-k delamination, because system constraints are fundamentally different from component-level ones.

The conclusion is clear: component-level qualification is no longer enough. TSMC does not just want you to buy its packaging; it wants you to hand over your system know-how and design the package together. This is a redistribution of influence: the packaging house is upgraded from "contract assembler" to the central node of system co-optimization.

4. The Line Hidden in the Talk: TSMC Confirms That Light Is the Future of AI Signaling

For STT readers, the talk contained one line not to be missed. Discussing the evolution of the interposer, Jun He said silicon electronics have always been great at computing, but when it comes to signaling, photons are far more power-efficient, and that is the future of the AI revolution.

The weight of that statement comes from where it was said. This was not an optical module maker waving the flag for its own business; it was the world's largest foundry and packaging house telling the systems camp that "optics in, copper out" is the settled direction. Combined with another point he made at the same time, that the interposer no longer just provides connectivity but is starting to integrate active bridges, integrated voltage regulators (IVR) and capacitors, the 3DIC TSMC describes is a system that packages compute dies, HBM, power delivery and optical I/O all together.

This is exactly the road TSMC's own silicon photonics strategy is paving. We broke down what TSMC's 52 silicon photonics patents are really doing in TSMC's 52 Silicon Photonics Patents Are All Doing the Same Thing: the answer is "an entire optical path," i.e., its COUPE platform aims to bring the optical engine inside advanced packaging. The OCP line that "signaling belongs to light" is the first time the intent behind those patents has been stated publicly at an industry-standards venue. For the entire CPO and silicon photonics supply chain, this is the highest-level endorsement possible.

5. Risks and Counterpoints: TSMC Does Not Get to Decide This Alone

Having laid out the trend, we also have to be honest about the bottlenecks that remain unsolved; otherwise this becomes cheerleading for TSMC.

The first bottleneck is substrates. Jun He himself acknowledged an industry-wide materials shortage, especially a severe shortage of ABF substrates, which has pushed customer procurement teams into risky multi-sourcing. The consequence: substrates from different sources often have inconsistent properties, so the material commonality reaching TSMC's CoWoS process actually gets worse, and the yield pressure lands back on packaging. This is a structural gap that even TSMC cannot close, and it bears on the bargaining power of Taiwanese substrate suppliers such as Unimicron and Nan Ya PCB. For why glass substrates are arriving all at once in 2026, see the full context in Glass Substrates Are No Longer a PowerPoint Technology.

The second bottleneck is thermal and mechanical stress. As packages place components with different thermal expansion and chemical properties ever closer together, what Jun He calls "mismatched gradients" build up significant stress. Once reticle size exceeds 5.5x, the problem goes from "imperceptible" to "visibly changing the story": the difficulty of heat dissipation and warpage rises nonlinearly.

The third bottleneck is whether STCO can actually work. TSMC is asking the systems camp to hand over boundary conditions, provide continuous feedback and station people next to the fab. It sounds great, but for customers it is a huge commitment of resources and confidential information. Probably only the handful of top AI customers are willing to bind themselves this tightly; second-tier customers may not be able to afford it. The annual cadence may actually accelerate industry concentration at the top.

Conclusion

This talk should not be read as "TSMC flexing its packaging muscles again." The real signal is that the bottleneck of AI compute has moved from the transistor to the step that packages chips, memory, power delivery and optics together, and TSMC intends to use that position to rewrite the collaboration rules of the entire supply chain, upgrading from component-level qualification to system-technology co-optimization.

For Taiwan's supply chain, this means two things. First, value is shifting toward "those who can sit next to the fab and co-optimize": substrates, materials, test, thermal, FAU and optical coupling, links long treated as supporting players. Whoever can station boots-on-the-ground expertise next to TSMC gets upgraded from supplier to co-development partner. Second, TSMC itself has defined light as the future of AI signaling. For the entire Taiwanese CPO and silicon photonics chain (lasers, FAU, SiPh foundry, optical coupling), this is the strongest demand-side confirmation yet.

In one sentence: the era of component-level qualification is over, and the next race is about who can package the system together with TSMC. Those who make it to the table will capture the richest value of this AI packaging cycle; those who don't will remain replaceable part numbers.

This article is for technology and industry trend analysis only and does not constitute investment advice.